Patents by Inventor Karen A. Szypulski

Karen A. Szypulski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9531647
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from multiple hosts, manages traffic among the hosts, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 27, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Gregg A. Bouchard, Troy S. Dahlmann, Jeffrey Richard Hardesty, Karen A. Szypulski
  • Patent number: 9497117
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: November 15, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Gregg A. Bouchard, Jeffrey R. Hardesty, Troy S. Dahlmann, Karen A. Szypulski
  • Patent number: 9276846
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. Based on information in the packet, the lookup front-end can optimize start times for sending key requests as a continuous stream with minimal delay. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 1, 2016
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Gregg A. Bouchard, Karen A. Szypulski, Charles D. Spackman
  • Patent number: 9152494
    Abstract: In an embodiment, a method of handling data packets within a processor includes intercepting, by a hardware packet integrity checking module, one or more data fields associated with a current segment of a data packet being forwarded from a first hardware entity operating in a cut-through mode to one or more processing clusters, where at least one data field of the one or more data fields is indicative of an operation associated with the data packet. At the hardware error detection module, integrity of the current segment of the data packet is checked based on the one or more data fields and parameters corresponding to the operation associated with the data packet. At least one data field of the one or more data fields is modified upon detecting an integrity error. The data fields are forwarded to the one or more processing clusters.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 6, 2015
    Assignee: Cavium, Inc.
    Inventors: Jeffrey R. Hardesty, Troy S. Dahlmann, Karen A. Szypulski, Jeffrey A. Pangborn, Najeeb I. Ansari, Theodore H. Holler
  • Publication number: 20140269718
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. Based on information in the packet, the lookup front-end can optimize start times for sending key requests as a continuous stream with minimal delay. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Rajan Goyal, Gregg A. Bouchard, Karen A. Szypulski, Charles D. Spackman
  • Publication number: 20140281834
    Abstract: In an embodiment, a method of handling data packets within a processor includes intercepting, by a hardware packet integrity checking module, one or more data fields associated with a current segment of a data packet being forwarded from a first hardware entity operating in a cut-through mode to one or more processing clusters, where at least one data field of the one or more data fields is indicative of an operation associated with the data packet. At the hardware error detection module, integrity of the current segment of the data packet is checked based on the one or more data fields and parameters corresponding to the operation associated with the data packet. At least one data field of the one or more data fields is modified upon detecting an integrity error. The data fields are forwarded to the one or more processing clusters.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Cavium, Inc.
    Inventors: Jeffrey R. Hardesty, Troy S. Dahlmann, Karen A. Szypulski, Jeffrey A. Pangborn, Najeeb I. Ansari, Theodore H. Holler
  • Publication number: 20140188973
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.
    Type: Application
    Filed: November 18, 2013
    Publication date: July 3, 2014
    Applicant: Cavium, Inc.
    Inventors: Rajan Goyal, Gregg A. Bouchard, Jeffrey R. Hardesty, Troy S. Dahlmann, Karen A. Szypulski
  • Patent number: 8606959
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: December 10, 2013
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Gregg A. Bouchard, Jeffrey R. Hardesty, Troy S. Dahlmann, Karen A. Szypulski
  • Publication number: 20130036152
    Abstract: A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 7, 2013
    Applicant: Cavium, Inc.
    Inventors: Rajan Goyal, Gregg A. Bouchard, Jeffrey R. Hardesty, Troy S. Dahlmann, Karen A. Szypulski
  • Patent number: 7889659
    Abstract: Controlling a transmission rate of packet traffic includes receiving packets from a network processor. The packets are stored in a buffer associated with a processor. If an occupancy level of the buffer is greater than a predetermined threshold, it is determined that the processor is congested. A message is transmitted to the network processor indicating the processor is congested.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: February 15, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Rafael Mantilla Montalvo, Jorge Manuel Gonzalez, Nathan Allen Mitchell, Timothy F. Masterson, Stephen Charles Hilla, Karen A. Szypulski
  • Publication number: 20080253284
    Abstract: Controlling a transmission rate of packet traffic includes receiving packets from a network processor. The packets are stored in a buffer associated with a processor. If an occupancy level of the buffer is greater than a predetermined threshold, it is determined that the processor is congested. A message is transmitted to the network processor indicating the processor is congested.
    Type: Application
    Filed: April 16, 2007
    Publication date: October 16, 2008
    Applicant: Cisco Technology, Inc.
    Inventors: Rafael Mantilla Montalvo, Jorge Manuel Gonzalez, Nathan Allen Mitchell, Timothy F. Masterson, Stephen Charles Hilla, Karen A. Szypulski