Patents by Inventor Karen Yokum
Karen Yokum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11562116Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.Type: GrantFiled: July 7, 2020Date of Patent: January 24, 2023Assignee: International Business Machines CorporationInventors: Tharunachalam Pindicura, Yan Xia, Karen Yokum, Vivek Britto, Shricharan Srivatsan, Aishwarya Dhandapani
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Patent number: 11556365Abstract: A hardware request of an application is detected. The Application executes on a virtualized computer system. It is determined that the hardware request includes a counter. The counter is to be performed by the virtualized computer system. The counter includes a counter value. The hardware request is intercepted before the it is processed by a hypervisor that hosts the virtualized computer system. The interception is based on the determining the hardware request includes the counter. The counter value is saved in a secure memory. The secure memory is obscured from the hypervisor. A scrambled counter value is generated. The hardware request is updated with the scrambled counter value. After the hardware request is updated it is provided to the hypervisor.Type: GrantFiled: September 24, 2019Date of Patent: January 17, 2023Assignee: International Business Machines CorporationInventors: Debapriya Chatterjee, Bryant Cockcroft, John A. Schumann, Karen Yokum
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Patent number: 11475191Abstract: Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.Type: GrantFiled: May 15, 2019Date of Patent: October 18, 2022Assignee: International Business Machines CorporationInventors: Paul Umbarger, Debapriya Chatterjee, Karen Yokum, John A. Schumann, Bryant Cockcroft, Kevin Barnett
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Patent number: 11436013Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: GrantFiled: March 26, 2020Date of Patent: September 6, 2022Assignee: International Business Machines CorporationInventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
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Patent number: 11301392Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.Type: GrantFiled: October 6, 2020Date of Patent: April 12, 2022Assignee: International Business Machines CorporationInventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
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Patent number: 11243864Abstract: An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.Type: GrantFiled: September 17, 2019Date of Patent: February 8, 2022Assignee: International Business Machines CorporationInventors: Bryant Cockcroft, John A. Schumann, Debapriya Chatterjee, Larry Leitner, Kevin Barnett, Karen Yokum
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Publication number: 20220012393Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.Type: ApplicationFiled: July 7, 2020Publication date: January 13, 2022Inventors: Tharunachalam Pindicura, YAN XIA, KAREN YOKUM, VIVEK BRITTO, SHRICHARAN, AISHWARYA DHANDAPANI
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Patent number: 11157285Abstract: A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.Type: GrantFiled: February 6, 2020Date of Patent: October 26, 2021Assignee: International Business Machines CorporationInventors: Bryant Cockcroft, John A. Schumann, Karen Yokum, Vivek Britto, Debapriya Chatterjee
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Publication number: 20210247982Abstract: A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.Type: ApplicationFiled: February 6, 2020Publication date: August 12, 2021Inventors: Bryant Cockcroft, John A. Schumann, Karen Yokum, Vivek Britto, Debapriya Chatterjee
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Publication number: 20210089340Abstract: A hardware request of an application is detected. The Application executes on a virtualized computer system. It is determined that the hardware request includes a counter. The counter is to be performed by the virtualized computer system. The counter includes a counter value. The hardware request is intercepted before the it is processed by a hypervisor that hosts the virtualized computer system. The interception is based on the determining the hardware request includes the counter. The counter value is saved in a secure memory. The secure memory is obscured from the hypervisor. A scrambled counter value is generated. The hardware request is updated with the scrambled counter value. After the hardware request is updated it is provided to the hypervisor.Type: ApplicationFiled: September 24, 2019Publication date: March 25, 2021Inventors: Debapriya Chatterjee, Bryant Cockcroft, John A. Schumann, Karen Yokum
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Publication number: 20210081296Abstract: An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Inventors: Bryant Cockcroft, John A. Schumann, Debapriya Chatterjee, Larry Leitner, Kevin Barnett, Karen Yokum
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Patent number: 10942853Abstract: A method, computer program product, and computer system are disclosed that in one or more embodiments includes issuing, from an issuing processor in the computer system, an address translation invalidation instruction with a return marker, wherein the address translation invalidation instruction is to invalidate one or more address translation entries in one or more storage locations in the computer system and wherein the return marker comprises an instruction to return information to the issuing processor indicating the identity of each processor where an invalidated entry was located.Type: GrantFiled: December 20, 2018Date of Patent: March 9, 2021Assignee: International Business Machines CorporationInventors: John A. Schumann, Debapriya Chatterjee, Bryant Cockcroft, Lawrence Leitner, Karen Yokum
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Patent number: 10915456Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.Type: GrantFiled: May 21, 2019Date of Patent: February 9, 2021Assignee: International Business Machines CorporationInventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
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Publication number: 20210019262Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.Type: ApplicationFiled: October 6, 2020Publication date: January 21, 2021Inventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
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Patent number: 10896273Abstract: A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.Type: GrantFiled: October 12, 2018Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. Schumann, Debapriya Chatterjee, Bryant Cockcroft, Kevin Barnett, Piriya K. Hall, Paul Umbarger, Karen Yokum
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Publication number: 20200371951Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.Type: ApplicationFiled: May 21, 2019Publication date: November 26, 2020Inventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
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Publication number: 20200364313Abstract: Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.Type: ApplicationFiled: May 15, 2019Publication date: November 19, 2020Inventors: Paul Umbarger, Debapriya Chatterjee, Karen Yokum, John A. Schumann, Bryant Cockcroft, Kevin Barnett
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Publication number: 20200225952Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
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Patent number: 10705843Abstract: A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.Type: GrantFiled: December 21, 2017Date of Patent: July 7, 2020Assignee: International Business Machines CorporationInventors: Omesh Bajaj, Kevin Barnett, Debapriya Chatterjee, Bryant Cockcroft, Jamory Hawkins, Lance G. Hehenberger, Jeffrey Kellington, Paul Lecocq, Lawrence Leitner, Tharunachalam Pindicura, John A. Schumann, Paul K. Umbarger, Karen Yokum
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Publication number: 20200201767Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes issuing from one of a plurality of processors an address translation invalidation instruction with a return marker, wherein the address translation invalidation instruction is to invalidate one or more address translation entries in one or more storage locations in the computer system; broadcasting the address translation invalidation instruction to one or more storage locations of one or more of the other processors; invalidating an address translation entry located in a storage location of the one or more storage locations; and returning information on the invalidated address translation entry to the issuing processor.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: John A. Schumann, Debapriya Chatterjee, Bryant Cockcroft, Lawrence Leitner, Karen Yokum