Abstract: Embodiments of the present systems and methods may provide techniques that may provide unit-level test of an SUT, but which translates the unit-level test into a valid test of the SUT itself. For example, in an embodiment, a computer-implemented method for testing a system, the method may comprise analyzing the system to determine sub-components of the system and inputs to the sub-components, performing dynamic testing of the system and collecting pairs of inputs to the system and inputs to the sub-components, training a machine learning model to translate from inputs to the sub-components to inputs to the system input using the collected pairs of inputs to the system and inputs to the sub-components and performing sub-component level testing and translating the sub-component level testing to system level testing.

Abstract: Embodiments of the present systems and methods may provide techniques that may provide unit-level test of an SUT, but which translates the unit-level test into a valid test of the SUT itself. For example, in an embodiment, a computer-implemented method for testing a system, the method may comprise analyzing the system to determine sub-components of the system and inputs to the sub-components, performing dynamic testing of the system and collecting pairs of inputs to the system and inputs to the sub-components, training a machine learning model to translate from inputs to the sub-components to inputs to the system input using the collected pairs of inputs to the system and inputs to the sub-components and performing sub-component level testing and translating the sub-component level testing to system level testing.

Abstract: A method, apparatus and computer-implemented method, the method comprising: receiving a statechart comprising a complex feature; and replacing the complex feature with a transformed feature, thereby transforming the statechart to a second statechart, wherein replacing the complex feature comprises: creating an auxiliary variable or a default state; changing a value of the auxiliary variable at the beginning of the transformed feature and changing the value of the auxiliary variable again at its end; and taking a transition from the default state, such that the transition occurs in accordance with the value of the auxiliary variable.

Abstract: A method, apparatus and computer-implemented method, the method comprising: receiving a statechart comprising a complex feature; and replacing the complex feature with a transformed feature, thereby transforming the statechart to a second statechart, wherein replacing the complex feature comprises: creating an auxiliary variable or a default state; changing a value of the auxiliary variable at the beginning of the transformed feature and changing the value of the auxiliary variable again at its end; and taking a transition from the default state, such that the transition occurs in accordance with the value of the auxiliary variable.

Abstract: A method, apparatus and product for dominant state based coverage metric. The method comprising: determining whether all possible states of a computer program were examined based on an analysis of states that were examined excluding controlled states that are dominated by a self-dominating states; wherein the controlled states are associated with a controlled nodes in a control flow graph of the computer program, wherein the self-dominating states are associated with a self-dominating node in the control flow graph; wherein each execution path in the control flow graph that reaches the controlled nodes also includes the self-dominating node; and wherein there exists an execution path in the control flow graph that both starts and ends at the self-dominating node and further includes at least one controlled node.

Abstract: A method, system and computer program product for creation of specification properties for a visual model of a system. The specification properties are useful for verification of a verification model corresponding to the visual model. The computer-implemented method comprising automatically generating, by a processor, a specification property for a verification model based on a selection by a user of at least one element in a visual model, wherein the visual model defines a computerized system, wherein the verification model corresponds to the visual model.

Abstract: A method, apparatus and product for dominant state based coverage metric. The method comprising: determining whether all possible states of a computer program were examined based on an analysis of states that were examined excluding controlled states that are dominated by a self-dominating states; wherein the controlled states are associated with a controlled nodes in a control flow graph of the computer program, wherein the self-dominating states are associated with a self-dominating node in the control flow graph; wherein each execution path in the control flow graph that reaches the controlled nodes also includes the self-dominating node; and wherein there exists an execution path in the control flow graph that both starts and ends at the self-dominating node and further includes at least one controlled node.

Abstract: A method, apparatus and computer program product for automatic parity check identification. The method comprising: automatically identifying a parity signal in a circuit design, wherein the parity signal is defined as a parity function of a set of support signals, wherein the automatic identification comprises: obtaining a candidate parity signal and a corresponding set of candidate support signals; and verifying that a bit flip in exactly one of any of the corresponding candidate set of support signals induces a bit flip on a value of the candidate parity signal; wherein said method further comprises reporting the automatically identified parity signal.

Abstract: A method, apparatus and computer program product for automatic parity check identification. The method comprising: automatically identifying a parity signal in a circuit design, wherein the parity signal is defined as a parity function of a set of support signals, wherein the automatic identification comprises: obtaining a candidate parity signal and a corresponding set of candidate support signals; and verifying that a bit flip in exactly one of any of the corresponding candidate set of support signals induces a bit flip on a value of the candidate parity signal; wherein said method further comprises reporting the automatically identified parity signal.

Abstract: Clock gating circuit is determined by transforming a clock gating opportunity function to a non-Boolean function and constraining inputs of the non-Boolean function. The non-Boolean function may be a ternary function. Constraining the inputs may be achieved by introducing control variables and a cardinality constraint associated with their values. The non-Boolean function may be utilized to approximate universal quantification of an input assigned with a non-Boolean value, such as “don't care” value. The non-Boolean function may be utilized to provide an ALL SAT solution of a Boolean function using a SAT solver.

Abstract: Clock gating circuit is determined by transforming a clock gating opportunity function to a non-Boolean function and constraining inputs of the non-Boolean function. The non-Boolean function may be a ternary function. Constraining the inputs may be achieved by introducing control variables and a cardinality constraint associated with their values. The non-Boolean function may be utilized to approximate universal quantification of an input assigned with a non-Boolean value, such as “don't care” value. The non-Boolean function may be utilized to provide an ALL SAT solution of a Boolean function using a SAT solver.

Abstract: A method to verify a circuit design may include applying a bounded model checking technique to a first computer language representation of the circuit design and to a second computer language representation of the circuit design. The method may also include determining a behavioral consistency between the first and second computer language representations.

Abstract: A computer-implemented method for solving a satisfiability (SAT) problem includes defining a formula, including variables, which refers to properties of a target system. Using a chosen search strategy, a search process is performed over possible value assignments of the variables for a satisfying assignment that satisfies the formula. A performance metric estimating an effectiveness of the search process is periodically evaluated during the search process. The strategy of the search process is modified responsively to the evaluated performance metric. The method determines, using the search process, whether the formula is satisfiable on the target system.

Abstract: A method to verify a circuit design may include applying a bounded model checking technique to a first computer language representation of the circuit design and to a second computer language representation of the circuit design. The method may also include determining a behavioral consistency between the first and second computer language representations.