Abstract: Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

Abstract: Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

Abstract: A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way.

Abstract: The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.

Abstract: The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.

Abstract: A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, comprises the steps of: writing test data words in parallel to the rows of the plurality of memory blocks; reading out test data words in parallel from the rows of the plurality of memory blocks to a corresponding plurality of on-chip data word comparators; presenting corresponding expected data words in parallel to the plurality of on-chip data word comparators for comparison with the read out data words of the corresponding memory blocks; concurrently comparing corresponding data bits of the read out data words and expected data words in corresponding data bit comparators to generate a column status bit for each data bit comparison; latching the column status bit of a mismatch bit compa

Abstract: A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way.

Abstract: During generation of a test case, in response to a predictable interrupt condition a dynamic portion of a dynamic trap handler is created. The static portion of the dynamic trap handler is generic trap handler code that is not dynamically created and performs such routine tasks as loading the trap number of the interrupt condition, loading a trap code pointer and preparing the processor to branch to the location pointed to by the trap code pointer. The dynamic portion of the trap handler, however, is dynamically created in response to each interrupt condition which occurs. The unique series of instructions of the dynamic portion of the trap handler may be tailored as desired to perform any number of tasks, including verifying the trap handler, verifying trap parameters, generating code to return to a new location upon completion of the trap handler, fixing the interrupt condition, updating the trap vector table, and updating the trap code pointer and a trap data pointer.

Abstract: In a conventional random test generator, instructions are generated, pushed onto a queue, and then popped off of the queue in generation order. The methods and apparatus disclosed herein provide a means of associating a delay with each generated instruction. Instructions are therefore popped off of the queue in response to their associated delay, rather than in generation order. Since the delay associated with each instruction of a synthesizing sequence (e.g., a load sequence) is randomly generated, a synthesizing sequence may be generated numerous times, yet never appear as the same sequence of instructions to a device under test. Furthermore, no register is reserved for a special purpose. As a result, the disadvantages of conventional instruction generating techniques are overcome.