Abstract: Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Abstract: The present invention is directed to a method and apparatus for synchronizing one or more data signal lines of a data bus to multiple clocks, and for guaranteeing the validity of the synchronized values. Exemplary embodiments avoid the need to eliminate delays between the asynchronous clocks. Thus, exemplary embodiments of the present invention can be used for reliably synchronizing the in-pointer and out-pointer of a first-in first-out memory.

Abstract: A circuit eliminates clock skew between an off-chip clock signal originating off an integrated circuit and an on-chip clock signal produced on the integrated circuit. The on-chip clock signal is produced by phase delaying the off-chip clock signal. A first delay path and a second delay path each phase delay the off-chip clock signal an identical amount. A multiplexor selects one of the delay paths to produce the on-chip clock signal. When phase delay through the first delay path is adjusted, the multiplexor selects the second delay path. When phase delay through the second delay path is adjusted, the selection means selects the first delay path. A phase detector and filter circuit generates control signals which indicate, based on phase difference between the off-chip clock signal and the on-chip clock signal, when to increase and when to decrease the phase delay through the delay paths.

Abstract: A FIFO memory circuit with improved read-access time includes an output register, which is connected to the data output terminal of the FIFO. The output register is clocked to provide the output of the FIFO with only the clock-to-output delay of the register. The FIFO memory circuit is formed with a series of latches, each of which latch has a data-input terminal connected in parallel to the data input terminal of the FIFO. Each latch has a tri-state output which is connected to an output terminal for the FIFO. Write-pointers select the next-available one of the FIFO locations to be read into. Read pointers select the next FIFO location to be read from. An input storage register is also provided to improve the input access time of the FIFO.