Patents by Inventor Karl Grant Hoebener

Karl Grant Hoebener has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6504105
    Abstract: High melting temperature Pb/Sn 95/5 solder balls are connected to copper pads on the bottom of a ceramic chip carrier substrate by low melting temperature eutectic Pb/Sn solder. The connection is made by quick reflow to prevent dissolving Pb into the eutectic solder and raising its melting temperature. Then the module is placed on a fiberglass-epoxy circuit board with the solder balls on eutectic Pb/Sn solder bumps on copper pads of the board. The structure is reflowed to simultaneously melt the solder on both sides of the balls to allow each ball to center between the carrier pad and circuit board pad to form a more symmetric joint. This process results in structure that are more reliable under high temperature cycling.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: January 7, 2003
    Assignee: International Business Machines Corporation
    Inventors: John Acocella, Donald Ray Banks, Joseph Angelo Benenati, Thomas Caulfield, Karl Grant Hoebener, David P. Watson, John Saunders Corbin, Jr.
  • Patent number: 5825629
    Abstract: A product created through the reflow of low melting point solder on select contacts of a printed circuit board. In one form, the printed circuit board has fine pitch devices, including flip-chip integrated circuits, connected to a board having conventional coarse pitch surface. The fine pitch contacts of the board are exposed through holes in a stencil characterized in its ability to withstand solder reflow temperatures, not be wettable by solder, and have a coefficient of thermal expansion relatively matching the printed circuit board. Low temperature solder paste is screen deposited into the stencil openings. With the stencil fixedly positioned on the board, the solder paste retained by the stencil pattern is reflowed to selectively form on the underlying contacts of the printed circuit board. Thereafter, the stencil is removed from the board and the board is subject to previously practiced depositions of flux and paste in preparation for fine and coarse pitch component placement and ensuing solder reflow.
    Type: Grant
    Filed: September 9, 1996
    Date of Patent: October 20, 1998
    Assignees: International Business Machines Corporation, Motorola, Inc.
    Inventors: Karl Grant Hoebener, Eric Max Hubacher, Julian Peter Partridge
  • Patent number: 5758413
    Abstract: A method of manufacturing a multiple layer circuit board with stacked vias of fine dimension and pitch. A base laminate with conductive pattern is coated with a dielectric which is photolithographically processed to create holes exposing selected regions of the underlying conductive pattern. The holes through the dielectric are plated to form via connections between the surface and the conductive pattern on the base laminate. The recess created by the via is filled with a conductive and plateable polymer which upon curing forms a conductive plug. A second dielectric layer is deposited on the board structure and in succession photolithographically processed to expose the underlying plated via and plug. The hole in the second dielectric is plated and filled with conductive polymer so as to create a second via vertically aligned with and electrically connected to the underlying first via.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Ku Ho Chong, Charles Hayden Crockett, Jr., Stephen Alan Dunn, deceased, Karl Grant Hoebener, Michael George McMaster
  • Patent number: 5699613
    Abstract: A method of manufacturing a multiple layer circuit board with stacked vias of fine dimension and pitch. A base laminate with conductive pattern is coated with a dielectric which is photolithographically processed to create holes exposing selected regions of the underlying conductive pattern. The holes through the dielectric are plated to form via connections between the surface and the conductive pattern on the base laminate. The recess created by the via is filled with a conductive and plateable polymer which upon curing forms a conductive plug. A second dielectric layer is deposited on the board structure and in succession photolithographically processed to expose the underlying plated via and plug. The hole in the second dielectric is plated and filled with conductive polymer so as to create a second via vertically aligned with and electrically connected to the underlying first via.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: December 23, 1997
    Assignee: International Business Machines Corporation
    Inventors: Ku Ho Chong, Charles Hayden Crockett, Jr., Stephen Alan Dunn, deceased, Karl Grant Hoebener, Michael George McMaster
  • Patent number: 5675889
    Abstract: Two substrates are produced each with a planar, mirror-image matrix of metal contacts in a surface wiring layer. The substrates are positioned with the matrices in parallel confrontation which defines pairs of confronting contacts. A metal ball is positioned between each pair of contacts with a respective volume of joining material between the ball and each of the two respective contacts. The volumes of joining material are simultaneously melted to allow surface tension to align the substrates and to accurately center the balls between each respective pairs of contacts in a plane defines by the matrix of balls.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 14, 1997
    Assignee: International Business Machines Corporation
    Inventors: John Acocella, Donald Ray Banks, Joseph Angelo Benenati, Thomas Caulfield, John Saunders Corbin, Jr., Karl Grant Hoebener, David P. Watson