Abstract: This invention is a data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and a data transfer section. These instruction sections are independent and may include differing options. In the preferred embodiment, each instruction is 64 bits. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit (110) includes a multiplication unit (220) and an arithmetic logic unit (230). The data unit (110) may include a barrel rotator (235) for one input of the arithmetic logic unit (230). The rotated data may be stored in the first destination register instead of the multiply result. The address unit (120) operations according to the data transfer operation field. This could be a load, a store or a register to register move.

Abstract: The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.

Abstract: The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.

Abstract: The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.

Abstract: The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.

Abstract: The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.

Abstract: The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.

Abstract: The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.

Abstract: The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.

Abstract: The present invention provides a digital backplane and various methods, systems and devices for controlling a digital backplane and light modulating elements. In some embodiments of the present invention, a recursive feedback method is used to control a digital backplane and/or light modulating elements and/or spatial light modulators.

Abstract: A method of manufacturing integrated circuits uses an architecture having multiple processors and multiple memories, such that there is at least first and second groups of processors and memories. The first group has at least a first processor and at least a first memory. The second group has at least a second processor and at least a second memory. Regardless of where the architecture is sliced, the integrated circuits have a majority of the same address and data pin-outs.

Abstract: A method of manufacturing integrated circuits uses an architecture having multiple processors and multiple memories, such that there is at least first and second groups of processors and memories. The first group has at least a first processor and at least a first memory. The second group has at least a second processor and at least a second memory. Regardless of where the architecture is sliced, the integrated circuits have a majority of the same address and data pin-outs.

Abstract: A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code.

Abstract: The present invention involves an improvement in color palettes which translate pixel color codes into color data words which have differing bits. In the color palette a stream of pixel color codes from a pixel map memory enables sequential selection of one of a set of color registers. The color data word stored in the selected color register controls the color of the current pixel within the video display. The innovation of the present invention is providing at least one color data word within the color palette which has no corresponding color of its own but which enables a repetition of the previous color. The entire visual image can be redefined by merely changing the pixel color codes at the first scanned edges of color regions if the entire pixel map memory is filled with pixel color codes which refer to repeat color data words. Hidden objects formed in the pixel map memory can be made to appear or disappear by redefining the color data words in the color registers.

Abstract: The present invention loads color registers of a color look up table in a color palette and recalls color data words from the color registers using only a single set of address and data channels. The color palette operates in two modes. In a normal mode one color code from a stream of pixel color codes received from a pixel map memory is employed to select one of the color registers. These color registers store color data words which define colors. A color data word stored in a selected color register is recalled and employed to control the color of a pixel on a raster scan video display. In a color look up table load mode, a predetermined number of the pixel color codes are loaded into the color look up table in a predetermined sequence, thereby defining a new set of colors. This technique multiplexes the existing data and control lines from the memory to the color palette for the two modes.

Abstract: The graphics data processing apparatus performs graphic data processing operations by combining data from two image arrays in accordance with a predetermined operation. This raster operation involves forming an image array having a pixel color code for each pixel of the combined image array formed from a combination of the color codes of corresponding pixels of the source and destination image arrays. The present invention includes a pair of data registers which define the difference in memory address between vertically adjacent pixels for the respective image arrays. This difference in memory address between vertically adjacent pixels is called the pitch and corresponds generally to the width of the display image in address space when any horizontal blanking interval is taken into account. In the present invention such raster operations can be performed on data which is stored in formats of differing pitch.