Abstract: A programming language for representing processes as strings of symbols has a syntax delimiting places in a symbol string. A convention associates delimited places in symbol strings. An invocation construct instantiated as an invocation string. A definition construct instantiated as a definition. Completeness of input of the invocation destination list is sufficient for resolving the process defined by a definition string.

Abstract: An array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data.

Abstract: Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data.

Abstract: Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data.

Abstract: A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Abstract: A switching element and method for asynchronous logic switches an output signal according to a switching-logic relationship between or among input signals. Input signals may assume at least a DATA value, a NULL value, and an INTERMEDIATE value. Input signals may also assume multiple DATA values. The element and method generates an output which assumes a NULL value when all input signals are NULL, and assumes DATA and INTERMEDIATE values in accordance with transform rules. Output signals may also assume an INTERMEDIATE value. DATA, NULL and INTERMEDIATE values may be encoded on to a number of signal lines. Transform rules may be threshold switching rules, where the output switches to a DATA output when a number of DATA inputs is greater than a threshold.

Abstract: An invocation architecture for generally concurrent process resolution comprises a plurality of interconnected processors, some of the processors being homogeneous processors and others of the processors being special purpose processors. Each homogeneous processor being capable of invoking a connected processor to have the connected processor resolve instructions. Each processor capable of being invoked by a connected processor to resolve instructions at the invocation of the connected processor.

Abstract: An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line based upon an evaluation of at least one data input value and an acknowledgment collection circuit, embedded in the data threshold circuit, for collecting a plurality of acknowledge signals and resolving the acknowledge signals for controlling, in combination with the at least one data input value, the passing of the data or NULL values to the output signal line. The acknowledgment collection circuit includes an M of N acknowledge collection circuit, wherein N is an integer representing the number of acknowledge signals being resolved and M representing a threshold, wherein M.ltoreq.N.

Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which is programmed to function as a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume a DATA state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of DATA inputs exceeds the threshold value. The gate preferably exhibit hysteresis such that the output remains DATA while the number of DATA inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, and array of simplified threshold elements is used to form more complex threshold gates.

Abstract: A threshold gate with registration embedded in the threshold logic is disclosed. A go-to-NULL network and a go to-data network receives data input having an asserted state and a NULL state. A directive or acknowledge signal is received by the embedded registrations network. The directive signal indicates whether an asserted state or the NULL state is desired at the output signal line. A data processing network is coupled to the go-to-NULL network to provide an output signal based upon the go-to-NULL network, the go-to-data network and the registration network. The go-to-data network provides a network of switches that cause an asserted state at the output signal line when a number of the data inputs in the asserted state exceeds a predetermined threshold and the acknowledge signal is in the asserted state. The go-to-NULL network provides a network of switches that cause a NULL state at the output signal line when all of the data inputs are in the NULL state and the acknowledge signal is in the NULL state.

Abstract: An invocation architecture for generally concurrent process resolution comprises a plurality of interconnected processors, some of the processors being homogeneous processors and others of the processors being special purpose processors. Each homogeneous processor being capable of invoking a connected processor to have the connected processor resolve instructions. Each processor capable of being invoked by a connected processor to resolve instructions at the invocation of the connected processor.

Abstract: A NULL convention logic bus includes: a plurality of bus transmission lines; a plurality of NULL convention transmitter ports; and a plurality of NULL convention receiver ports. Each NULL convention transmitter port propagates alternating wavefronts of data an NULL across the bus transmission lines to a NULL convention receiver port. A pipeline bus includes NULL convention storage registers at the transmitter ports. A FIFO pipeline bus includes NULL convention storage registers at the receiver ports. A NULL convention register file includes: a NULL convention input register; and a plurality of NULL convention storage registers. The input register synchronously propagates alternating wavefronts of NULL and data to an addressed NULL convention storage register.

Abstract: A NULL convention logic element comprises an input, an output and a threshold switching circuit. The input receives NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The output produces output NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The threshold switching circuit triggers changes of the output signal state to NULL in response to the states of all the input signals becoming NULL.

Abstract: A method and system for process expression and resolution is described. A first language structure comprising a possibility expression having at least one definition which is inherently and generally concurrent is provided. Further, a second language structure comprising an actuality expression including a fully formed input data name to be resolved is provided. Furthermore, a third language structure comprising an active expression initially having at least one invocation, the invocation comprising an association with a particular definition and the fully formed input data name of the actuality expression is provided. Subsequently, the process of resolving invocations begins in the active expression with fully formed input data names in relation to their associated definition to produce at least one or both of the following: (1) an invocation with a fully formed input data name and (2) a result data name.

Abstract: A NULL convention logic bus includes: a plurality of bus transmission lines; a plurality of NULL convention transmitter ports; and a plurality of NULL convention receiver ports. Each NULL convention transmitter port propagates alternating wavefronts of data an NULL across the bus transmission lines to a NULL convention receiver port. A pipeline bus includes NULL convention storage registers at the transmitter ports. A FIFO pipeline bus includes NULL convention storage registers at the receiver ports.

Abstract: A NULL convention full adder receives a plurality of inputs, each having an asserted state and a NULL state. The adder switches its output to an asserted state when all inputs have been received and summed. The adder switches its output to the NULL state only after all inputs have returned to NULL. A register can be incorporated into each full adder. Multiple full adders are combined into multi-bit adders with registration.

Abstract: An interface circuit between NULL Convention Logic and non-NULL convention memory includes: a first conversion circuit which converts NULL convention address signals to non-NULL address signals. A non-NULL convention memory circuit, e.g., a conventional binary memory, generates non-NULL data signals in response to the non-NULL address signals. A second conversion circuit converts the non-NULL data signals to NULL convention data signals. A timing circuit controls DATA and NULL wavefronts to and through the non-NULL memory.

Abstract: A Null convention logic system for processing NULL convention signals is comprised of interconnected processing elements. NULL convention signals can assume at least a first meaningful value indicating data and a NULL value which has no data significance. Processing elements receive a plurality of NULL convention signals and produce a meaningful output data value when the number of meaningful input data values exceeds a threshold number. The gates assert a NULL output when all inputs are in the NULL state. Processing elements exhibit hysteresis such that, as the number of meaningful input values falls below the threshold number, the element holds a meaningful output value (or a non-data non-NULL value) until all inputs are in the NULL state. The threshold number may be less than the total number of inputs. Groups of elements may be interconnected, and thresholds selected, to perform logic and other processing functions asynchronously on meaningful signal values.

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Abstract: A NULL convention threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.