Abstract: A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.

Abstract: A method for forming a sum of the absolute value of the difference between each pair of numbers of respective first and second sets of numbers. The method includes forming the difference between corresponding numbers of the first and second sets. This difference is either added to or subtracted from a running sum based upon its sign. This is repeated for all number pairs. Preferably, the initial subtraction sets a status bit in a flag register (211) which controls the selection of addition or subtraction. The conditional addition to or subtraction from the running sum may generate a carry-out representing the most significant bit of the running sum. This carry-out is preferably stored and later added to the running sum to recover the most significant overflow bits. This technique is preferably practiced using an arithmetic logic unit (230) that can be split into plural independent sections (301, 302, 303, 304).

Abstract: A multilevel hierarchical least recently used cache replacement priority in a digital data processing system including plural memories, each memory connected to said system bus for memory access, a memory address generator generating addresses for read access to a corresponding of the memories and a memory cache having a plurality of cache entries, each cache entry including a range of addresses and a predetermined set of cache words. During each memory read the comparator compares the generated address with the address range of each cache entry. If there is a match, then the cache supplies a cache word corresponding to the least significant bits of the generated address from the matching cache entry. If there is no such match, the generated address is supplied to the memories and a set of words is recalled corresponding to the generated address. This set of words replaces a least recently used prior stored memory cache entry having the lowest priority level.

Abstract: The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A data processing apparatus having an arithmetic logic unit (230) with conditional register source selection includes a plurality of data registers (200), a status register (210) storing at least one status bit, an arithmetic logic unit (230) and an instruction decode logic (245, 246, 250). The instruction decode logic (245, 246, 250) responds to a received register pair conditional source instruction to supply data from either a first register or a second register to the first input of said arithmetic logic unit (230) depending on the digital state of a status bit. Preferably an instruction field indicates whether the instruction involves conditional register pair source selection. There are preferably a plurality of status bits and the register pair conditional source instruction determines which status bit controls the source selection. A prior output of the arithmetic logic unit (230) sets the plural status bits. These may include negative, carry, overflow and zero.

Abstract: A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.

Abstract: Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation.

Abstract: This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input.

Abstract: The invention involves communication within a multiprocessor system. The multiprocessor system includes a command word bus and a plurality of data processors. Each data processor is connected to the command word bus and includes a command circuit, a decoder and a reset control circuit. The command circuit may generate a command word on the command word bus including at least one reset command word for resetting a data processor. The decoder decodes command words received via the command word bus and includes at least a reset command decoder for decoding a reset command word. The reset control circuit resets the data processor into a state corresponding to initial application of electrical power upon receiving a reset command word. Each command word circuit generates command words indicating a particular data processor to which it is directed. Only a predetermined subset of the data processors may send the reset command word directed to other data processors.

Abstract: An address generator (120) forms a selective merge of two addresses. First (610) and second (620) address units generate respective first and second N bit address. Each unit (610, 620) preferrably includes a set of base address registers (611), a set of index address registers (612) and a full adder (615). Each address unit (610, 620) selects one of the base address registers (611) and one of the index address registers (612) according to the current instruction. The full adder (615) selectively adds the index address to the base address or subtracts the index address from the base addess according to the current instruction. An address multiplexer register (630) stores an N bit multiplex word.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

Abstract: A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store data in a first register into memory if a selected status bit has a first state and to store data in a second register associated with the first register into memory if the selected status bit has a second state in response to a register pair conditional store instruction. The bits may indicate a negative output of the arithmetic logic unit (230), a carry out signal, an overflow, or a zero output. The register pair conditional store instruction designates a particular one of the status bits to control the conditional store. The instruction logic circuit (250, 660) substitutes the selected status bit for a least significant bit of the register number. Thus memory store is from the first register if the status bit is "1" and is from the second register if the status bit is "0".

Abstract: This invention involves computing a mean squared error between a predetermined plural number of pairs of first and second values. A data processing apparatus (71, 72, 73, 74) has data registers (200), an arithmetic logic unit (230), a flags register (211), a multiplication unit (220), a source of instructions and an instruction decoder (245, 246, 250). The arithmetic logic unit (230) forms a difference between pairs. The flags register (211) stores status bits indicating whether the result is less than zero. The arithmetic logic unit (230) conditionally either adds the difference to zero if the status bit indicates the difference was not less than zero or subtracts the difference from zero if the status bit indicated the difference was less than zero. The multiplication unit (220) forms the square. The square is added to a running sum.

Abstract: A data processor includes both integer and floating point operation units and operates as a reduced instruction set computer (RISC). A modification of the normal load/store RISC operations includes within in its instruction set some instructions that permit floating point operations to be paired with load or store operations. These operations include: vector floating point add; vector multiply accumulate; vector floating point multiply; vector multiply subtract; vector reverse subtract; vector round floating point input; vector round integer input; and vector floating point subtract.

Abstract: This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values.

Abstract: This invention is an iterative technique for division. The divisor has N bits and the numerator has more than N bits, generally 2N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator in left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations of the division is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. If this is nonzero, then the numerator shifts this number of places and the corresponding quotient bits are set to "0". Next the division technique calculates the difference between the N most significant bits of the numerator and the divisor. If the difference is greater than or equal to zero, then the next quotient bit is "1".

Abstract: An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a flags register (211), which preferably includes more bits than the maximum number of sections of the arithmetic logic unit (230). New status signals may overwrite the previous status signals or rotate the stored bits and store the new status signals. A status register (210) stores a size indicator that determines the a number of sections of the arithmetic logic unit (230). A status detector has a zero detector (321, 322, 323, 324) for each elementary section (301, 302, 303, 304) of the arithmetic logic unit (230). When there are fewer than the maximum number of sections, these zero signals are ANDed (331, 332, 341). A multiplexer couples the carry-out of an elementary (311, 312, 313, 314) to the carry-in of an adjacent elementary section (301, 302, 303, 304) or not depending on the selected number of sections.