Abstract: A process for milling amorphous solids using a milling apparatus can result in particles having a median particle diameter d50 of <1.5 ?m. The process includes: operating a mill in a milling phase with an operating medium selected from the group consisting of gas, vapour, steam, a gas containing steam and mixtures thereof, and heating a milling chamber in a heat-up phase before the actual operation with the operating medium in such a way that a temperature in the milling chamber, the mill exit or both, is higher than a dew point of the operating medium.

Abstract: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

Abstract: Precipitated silicas having an SiOHisolated absorbance ratio of greater than or equal to 1, may be used as reinforcers and thickeners for sealants.

Abstract: A precipitated silica having an SiOHisolated absorbance ratio of greater than or equal to 1.5, a silanol group density of 1 to 3.0 SiOH/nm2, a modified tapped density of 1 to 50 g/l, and a pH of 3-5, when measured as a aqueous suspension of 5.00 g of the precipitated silica in 100 ml. of deionized water allows preparation of storage-stable RTV-1 silicone rubber formulations without stabilizer. A process for preparing the precipitated silica and its use in thickening sealants is provided.

Abstract: A precipitated silica having a d50-value of from 150 to 2000 nm, a d90-value of from 500 to 7000 nm, a silanol group density of from 2.5 to 8 OH/nm2, and a modified tapped density of less than or equal to 70 g/l is useful for thickening and providing thixotropy in liquid systems and shows superior efficiency at thickening and creating thixotropy compared to existing grades of precipitated silica. The precipitated silica functions best as a thixotrope in non-polar or intermediate polar liquid systems such as unsaturated polyester (UPE) resin systems.

Abstract: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.

Abstract: A process for milling amorphous solids using a milling apparatus can result in particles having a median particle diameter d50 of <1.5 ?m. The process includes: operating a mill in a milling phase with an operating medium selected from the group consisting of gas, vapor, steam, a gas containing steam and mixtures thereof, and heating a milling chamber in a heat-up phase before the actual operation with the operating medium in such a way that a temperature in the milling chamber, the mill exit or both, is higher than a dew point of the operating medium.

Abstract: Hydrophilic precipitated silicas which combine a particularly low initial moisture content with low moisture absorption over time, a low tapped density and a low silanol group density, have the following physicochemical parameters: equilibrium moisture content (at 70% relative humidity/20° C.) of 0.5%-5.0% by weight, based on the weight of the hydrophilic precipitated silica, BET surface area of 50-250 m2/g, CTAB surface area of 50-250 m2/g, and DBP (anhydrous) of 200-350 g/100 g.

Abstract: Precipitated silicas having an SiOHisolated absorbance ratio of greater than or equal to 1, may be used as reinforcers and thickeners for sealants.

Abstract: A precipitated silica having the following physico-chemical characteristics: pH (5% in water) (ISO 787-9) 3–8 BET surface area (DIN 66131) (m2/g) 400–600 DBP absorption value (DIN 53601, (g/100 g) 380–420 in relation to dried substance) Tapped density (ISO 787-11) (g/l) 100–200 ALPINE sieve residue > 63? (ISO 8130-1) (%) 0.1–40.

Abstract: The invention provides an interconnection architecture for semiconductor devices. Cross bar switches are traditionally placed in the center of the IC. However, this location may also be the preferred location for the centralized logic in the IC. This invention, known as a cross bar ring or CBR, provides cross bar switch functionality in a manner that can be easily distributed around the chip. Typically, it can fit in the routing channels between other functional blocks, thereby allowing other centralized functions to be placed in the center of the IC. The CBR is defined so that it can be partitioned into separate modules, which greatly aids in the placement and routing of wires. Furthermore, the architecture is defined such that the CBR can use storage elements, allowing it to be pipelined so that the wire distances can be increased while still maintaining a high internal clock speed.

Abstract: The present invention provides an improved apparatus and method for the receipt of high-speed sequential data streams. It utilizes the concept of banked memories to reduce the required speed and size of the input buffers used to receive the data streams. This allows the device to employ large, relatively slow memory elements, thereby permitting large amounts of sequential data to be stored by the receiving device. Using control information that was written as the data was being stored in the memory banks, a reordering element is later able to retrieve the data elements from the plurality of memory banks, in an order that is different from that in which the stream was received, and to reassemble the data stream into the original sequence.

Abstract: A hydrophobic precipitated silica is prepared by a process comprising: a) preparing a mixture of an organopolysiloxane derivative and a precipitated silica; b) conditioning the mixture obtained at a temperature ranging from 10 to 150° C. for a period ranging from 0.5 to 72 h, and c) conducting oxidative heat treatment under fluid conditions at a temperature more than 300° C. with an oxidizing gas.

Abstract: The invention provides an interconnection architecture for semiconductor devices. Cross bar switches are traditionally placed in the center of the IC. However, this location may also be the preferred location for the centralized logic in the IC. This invention, known as a cross bar ring or CBR, provides cross bar switch functionality in a manner that can be easily distributed around the chip. Typically, it can fit in the routing channels between other functional blocks, thereby allowing other centralized functions to be placed in the center of the IC. The CBR is defined so that it can be partitioned into separate modules, which greatly aids in the placement and routing of wires. Furthermore, the architecture is defined such that the CBR can use storage elements, allowing it to be pipelined so that the wire distances can be increased while still maintaining a high internal clock speed.

Abstract: An improved architecture for switches and a method for transmitting data with the switching are disclosed. An increased amount of memory is utilized, operating at speeds lower than are required by Input Queued switches, and a simple scheduling algorithm. The architecture divides the input ports into groups, where each input port group has an associated set of memory elements. Incoming packets are routed to the appropriate element in the set of memory elements. The number of groups and the number of ports that are included in each group can be varied, allowing the architecture to be modified based on the system architecture, the semiconductor technology, and other design considerations.

Abstract: Battery charging device and method for charging batteries by means of a power supply module, whereby a battery (30) comprises a plurality of battery blocks (31, 32, 33, . . . , 3n) connected in series. The individual battery blocks (31, 32, 33, . . . , 3n) of the battery (30) are charged serially one after the other, once per charging cycle for a definable duration, and the charging cycle is repeated so many times until the individual battery blocks (31, 32, 33, . . . , 3n) have reached a definable state of charge or until the power supply is broken. The invention relates in particular to methods and systems for charging batteries (30) in electric vehicles, among other things.

Abstract: The present invention minimizes the amount of traffic that traverses the fabric in support of the cache coherency protocol. It also allows rapid transmission of all traffic associated with the cache coherency protocol, so as to minimize latency and maximize performance. A fabric is used to interconnect a number of processing units together. The switches are able to recognize incoming traffic related to the cache coherency protocol and then move these messages to the head of that switch's output queue to insure fast transmission. Also, the traffic related to the cache coherency protocol can interrupt an outgoing message, further reducing latency. The switch incorporates a memory element, dedicated to the cache coherency protocol, which tracks the contents of all of the caches of all of the processors connected to the fabric. In this way, the fabric can selectively transmit traffic only to the processors where it is relevant.

Abstract: The invention utilizes a separate queue per output port as implemented in the traditional simple queuing schemes of the prior art. Further, it also uses the information found in the packet header to determine the output port and the next output port. Based on this information, it utilizes queues dedicated to congested flows, or “Congested Flow” queues. When the switch determines that, based on the first output port and the second subsequent output port, a packet in the output queue is destined for a congested path, it sets the offending packet aside in a Congested Flow queue, thereby allowing other packets destined for the first output port to continue to be transmitted. In this way, the HOL blocking issue is addressed, without the need for a significantly increased number of output queues.

Abstract: Precipitated silicas with a high pH and their use in applications as defoamers having optimum silanol group density and a process for preparing precipitated silicas and to their use, particularly in defoamer formulations.

Abstract: Hydrophobic precipitated silicas with a high pH and low silanol group density, a process for preparing them and their use, particularly in deformer formulations.