Abstract: A method of transmitting data in a redundant automation system, has a plurality of data transmission units and a plurality of data processing units. To possibly transmit in an especially efficient manner with the hardware resources available, a data flow characteristic of the data transmission is continuously monitored on the respective data transmission units, and depending on the data flow, data transmission is switched between the various operating modes in such a manner that an operating mode is adjusted when a synchronized data flow is detected on at least two data transmission units, the operating mode having a higher availability vis-à-vis the operating mode with a defective or one-way data flow on one of the data transmission units.

Abstract: The invention relates to method for transmitting data in a redundant automation system (2), comprising a plurality of data transmission units (6) and a plurality of data processing units (4). The aim of the invention is to improve said method in such a way that data can be transmitted in an especially efficient manner with the hardware resources available. To this end, a data flow characteristic of the data transmission is continuously monitored on the respective data transmission units (6) and, depending on the data flow, is switched between the various operating modes in such a manner that an operating mode is adjusted when a synchronized data flow is detected on at least two data transmission units (6), said operating mode having a higher availability vis-à-vis the operating mode with a defective or one-way data flow on one of the data transmission units (6).

Abstract: A buffer circuit of a decentralized peripheral module. The buffer circuit has three input and three output signal storage areas, which can be selectively connected to a bus interface or a module interface via a selection circuit. Thus the process signal transfer from an intelligent unit arranged on the module to a unit of a higher level than the module and vice-versa can be completely separated.

Abstract: A bus controller for an electronic device which has an intelligence (or processor) of its own and a memory having a plurality of individually addressable memory locations which are connected with each other via a system bus. The bus controller can be connected with at least the memory and a network bus. The network bus serves for networking several electronic devices with each other (including the electronic device). The bus controller manages at least one request-receipt queue with queue elements for requests to be received over the network bus, wherein the queue is organized as a double-linked list.