Patents by Inventor Karl W. Barth
Karl W. Barth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8349729Abstract: Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.Type: GrantFiled: March 13, 2012Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Karl W. Barth, Ricardo A. Donaton, Spyridon Galis, Kevin S. Petrarca, Shahab Siddiqui
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Patent number: 8236655Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.Type: GrantFiled: November 4, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee, Kevin S. Petrarca
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Publication number: 20120171818Abstract: Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karl W. Barth, Ricardo A. Donaton, Spyridon Galis, Kevin S. Petrarca, Shahab Siddiqui
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Patent number: 8159060Abstract: Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.Type: GrantFiled: October 29, 2009Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Karl W. Barth, Ricardo A. Donaton, Spyridon Galis, Kevin S. Petrarca, Shahab Siddiqui
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Patent number: 8089105Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.Type: GrantFiled: November 4, 2010Date of Patent: January 3, 2012Assignee: International Business Machines CorporationInventors: Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee, Kevin S. Petrarca
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Publication number: 20110101537Abstract: Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.Type: ApplicationFiled: October 29, 2009Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karl W. Barth, Ricardo A. Donaton, Spyridon Galis, Kevin S. Petrarca, Shahab Siddiqui
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Publication number: 20110045644Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.Type: ApplicationFiled: November 4, 2010Publication date: February 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee, Kevin S. Petrarca
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Publication number: 20110042779Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.Type: ApplicationFiled: November 4, 2010Publication date: February 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee, Kevin S. Petrarca
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Patent number: 7892926Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.Type: GrantFiled: July 24, 2009Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee, Kevin S. Petrarca
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Publication number: 20110018091Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.Type: ApplicationFiled: July 24, 2009Publication date: January 27, 2011Applicant: International Business Machines CorporationInventors: Karl W. Barth, Jeffrey P. Gambino, Tom C. Lee, Kevin S. Petrarca
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Patent number: 7851919Abstract: A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.Type: GrantFiled: February 5, 2010Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Karl W. Barth, Ramona Kei, Kaushik A. Kumar, Kevin S. Petrarca, Shahab Siddiqui
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Publication number: 20100133694Abstract: A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.Type: ApplicationFiled: February 5, 2010Publication date: June 3, 2010Inventors: Karl W. Barth, Ramona Kei, Kaushik A. Kumar, Kevin S. Petrarca, Shahab Siddiqui
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Patent number: 7718525Abstract: Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.Type: GrantFiled: June 29, 2007Date of Patent: May 18, 2010Assignee: International Business Machines CorporationInventors: Karl W. Barth, Ramona Kei, Kaushik A. Kumar, Kevin S. Petrarca, Shahab Siddiqui
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Patent number: 7541277Abstract: A method for forming a dielectric cap layer over an interconnect layer formed by a back-end-of-the-line (BEOL) interconnect process, the interconnect process including: lithography, reactive ion etching (RIE), metal filling of BEOL conductors, and chemical-mechanical polishing (CMP), wherein a sacrificial material resides between conductors of the interconnect layer, and wherein the dielectric cap layer is made porous through an oxidation process.Type: GrantFiled: April 30, 2008Date of Patent: June 2, 2009Assignee: International Business Machines CorporationInventors: Kevin Shawn Petrarca, John Charles Petrus, Karl W. Barth, Kaushik A. Kumar
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Publication number: 20090014868Abstract: Methods of manufacturing an IC chip in portions for later combining and a related structure are disclosed. In one embodiment, the method includes: fabricating a first portion of the IC chip, the first portion including a structure from a selected level of back-end-of-line (BEOL) processing up to an end of the BEOL processing, the first portion providing a specific functionality when combined with a second portion of the IC chip, fabricating the second portion of the IC chip, the second portion including a structure from a device level of the IC chip up to the selected level of the BEOL processing, the second portion having structure providing generic IC chip functionality. The fabrication of the portions may occur at a single location or different locations, and the combining may occur at the same location or different location as one or more of the fabrication processes.Type: ApplicationFiled: July 10, 2007Publication date: January 15, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karl W. Barth, Kaushik A. Kumar, Kevin S. Petrarca, Victoria J. Sternhagen
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Publication number: 20090001592Abstract: Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karl W. Barth, Ramona Kei, Kaushik A. Kumar, Kevin S. Petrarca, Shahab Siddiqui
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Patent number: 7101817Abstract: A apparatus and method for determining minimum line widths of free standing structures built by a semiconductor (S/C) manufacturing process. Free standing structures are created in a semiconductor device and subjected to an aerosol process which is tuned and centered with respect to a critical line width for the free standing structures. The S/C manufacturing process is tuned responsive to failure of free standing structures of sub-critical line widths.Type: GrantFiled: November 5, 2004Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Stephen M. Lucarini, Karl W. Barth, Stephen K. Loh