Abstract: Forming of filled isolation trenches, in particular the transition area in trenches and recesses free of silicon during the realization of MEMS structures of SOI wafers. A reliable dielectric insulation of adjacent silicon regions is to be obtained. The insulation is achieved by filled isolation trenches. The end portions of the trench fill that are freed from the surrounding silicon by etching are free of conductive not completely removed silicon strips in the recess including the active sensor structure. This is accomplished by slanted wall of isolation trenches. Additionally, the trench fill should be removable at the transition area in an efficient manner. The technological realization does not require specific additional process steps.

Abstract: Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO2 is formed by a CVD process with the oxide layers having increasing thickness toward the upper trench edges forming first bottlenecks. The first fill oxide layers are then RIE etched to initially remove the oxide layer from the wafer surface with continued etching to remove the oxide layers in upper trench portions to define later sealing portions of the voids or to displace the first bottlenecks downward to define further bottlenecks. A second SiO2 deposition is then performed using a low pressure CVD process to deposit oxide near steps formed previously and/or at the displaced bottlenecks to seal the voids. The deposition process is stopped when the sealed portions of the oxide layer above the voids are grown above the semiconductor wafer surface.

Abstract: A technique is provided which enables quantitative evaluation of an undercutting of deep trench structures in semiconductor wafers and, in particular, SOI wafers, by means of electrical or optical measuring. A specific control structure (100) having a defined ridge width is used which can be routinely measured in the course of the production process. The control structure comprises two adjacent trenches (5) each which are separated by a ridge having a defined ridge width. By undercutting (U) the adjacent trenches, the regions of undercutting of adjacent trenches may intersect each other starting from a specific minimum ridge width which results in a detachment of the ridge from the bottom making the ridge moveable. Mobility is determined by thermal deflection of the ridge. Arranging a plurality of control structures having various ridge widths enables determination of a quantitative amount of the undercutting.

Abstract: Insulating trenches isolate regions of a semiconductor layer and include hermetically sealed voids. After forming a trench, a first fill of SiO2 is formed by a CVD process with the oxide layers having increasing thickness toward the upper trench edges forming first bottlenecks. The first fill oxide layers are then RIE etched to initially remove the oxide layer from the wafer surface with continued etching to remove the oxide layers in upper trench portions to define later sealing portions of the voids or to displace the first bottlenecks downward to define further bottlenecks. A second Sio2 deposition is then performed using a low pressure CVD process to deposit oxide near steps formed previously and/or at the displaced bottlenecks to seal the voids. The deposition process is stopped when the sealed portions of the oxide layer above the voids are grown above the semiconductor wafer surface.

Abstract: A method for the electrical measurement of the thickness of a semiconductor layer ( 10, 11, 12) is disclosed. Active layers on SOI wafers, EPI layers with inverse conductivity tape and membrane thickness can be measured by use of a test structure which can routinely be measured during a production process. The embodiment of the test structure (A1 to F1) is preferably annular, such that a high degree of symmetry is achieved on propagation of the measuring current and such that no interactions occur with surrounding structures. The diameter of the arrangement can be matched to the corresponding thickness range of the semiconductor layer to be measured using conventional U-I parameter test systems, conventionally applied in semiconductor production. The determination of the layer thickness is achieved by means of two sequential quadrupole measurements at six contact points.

Abstract: Forming of filled isolation trenches, in particular the transition area in trenches and recesses free of silicon during the realisation of MEMS structures of SOI wafers. A reliable dielectic isulation of adajacent silicon regions is to be obtained. The insulation is achieved by filled isolation trenches (17). The end portions of the trench fill that are freed from the surrounding silicon by etching are free of conductive not completely removed silicon strips in the recess including the active sensor structure. This is accomplished by slanted wall of the isolation trenches (17). Additionally, the trench fill should be removable at the transition area in an efficient manner. The technological realisation does not require specific additional process steps.

Abstract: The invention relates to a method and an assembly for forming structures that are dielectrically insulated from each other by means of filled hermetically sealed isolation trenches for the formation of mechanical-electrical sensor structures, which require for their functioning a hermetically sealed cavity, in which are located the moveable sensor elements.