Abstract: Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system includes a quantum processor comprising a plurality of qubits. The system includes a light emitting source that can be tuned to produce light pulses of different wavelengths. The system includes an array of bandpass filters. Each bandpass filter is aligned with a qubit on the quantum processor and has a unique pass band. The system may include a controller configured to receive a selection of a qubit and to tune the light emitting source to emit a light pulse having a wavelength that falls within a range of a bandpass filter that is aligned with the selected qubit. The light pulse is used to scramble an ensemble of strongly coupled two-level system (TLS) in the processor.

Abstract: Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system includes a quantum processor having multiple qubits. The system includes an array of light emitting sources. Each light emitting source is aligned with a qubit on the quantum processor. The system includes a controller configured to receive a selection of a qubit and to enable a light emitting source from the array of light emitting sources to emit light to the selected qubit. The light is use to scramble strongly coupled two-level systems (TLSs) in the quantum processor.

Abstract: Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system uses an iterative process of applying light pulses and examining qubit relaxation times to eliminate or minimize two-level system (TLS) interaction with qubits. The system applies a first light pulse to illuminate a quantum processor having one or more qubits. The system receives qubit relaxation times that are measured at different electric field frequencies after applying the first light pulse.

Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.

Abstract: Embodiments of the present disclosure include methods of determining scribing offsets in a hybrid laser scribing and plasma dicing process. In an embodiment, the method comprises forming a mask above a semiconductor wafer. In an embodiment, the semiconductor wafer comprises a plurality of dies separated from each other by streets. In an embodiment, the method further comprises patterning the mask and the semiconductor wafer with a laser scribing process. In an embodiment, the patterning provides openings in the streets. In an embodiment, the method further comprises removing the mask, and measuring scribing offsets of the openings relative to the streets.

Abstract: A Junction Field Effect Transistor (JFET) has a source and a drain disposed on a substrate. The source and drain have an S/D doping with an S/D doping type. Two or more channels are electrically connected in parallel between the source and drain and can carry a current between the source and drain. Each of the channels has two or more channel surfaces. The channel has the same channel doping type as the S/D doping type. A first gate is in direct contact with one of the channel surfaces. One or more second gates is in direct contact with a respective second channel surface. The gates are doped with a gate doping that has a gate doping type opposite of the channel doping type. A p-n junction (junction gate) is formed where the gates and channel surfaces are in direct contact. The first and second gates are electrically connected so a voltage applied to the first and second gates creates at least two depletion regions in each of the channels.

Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.

Abstract: A steer by wire system includes at least a steering wheel actuator for operating steering wheel and steering column. The steering wheel actuates the steering wheel actuator by way of a brushless DC motor. The steering wheel actuator adjusts the steering column in a tilt direction by way of a first brushed DC motor and in a telescopic direction by way of a second brushed DC motor. The first brushed DC motor and the second brushed DC motor are configured to operate via two separate H bridges having a shared arm of switches. The brushless DC motor is configured to operate with two three-phase H bridges of which one three-phase H bridge is the network of switches of the first brushed DC motor and the second brushed DC motor.

Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.

Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.

Abstract: In an embodiment, a semiconductor processing tool for implementing hybrid laser and plasma dicing of a substrate is provided. The semiconductor processing tool comprises a transfer module, where the transfer module comprises a track robot for handling the substrate, and a loadlock attached to the transfer module. In an embodiment, the loadlock comprises a linear transfer system for handling the substrate. In an embodiment, the processing tool further comprises a processing chamber attached to the loadlock, wherein the linear transfer system of the loadlock is configured to insert and remove the substrate from the processing chamber.

Abstract: A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.

Abstract: A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.

Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.

Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.

Abstract: A Vertical Field Effect Transistor (VFET) and/or a one transistor dynamic random access memory 1T DRAM that has a substrate with a horizontal substrate surface, a source disposed on the horizontal substrate surface, a drain, and a channel. The channel has a channel top, a channel bottom, a first channel side, a second channel side, and two channel ends. The channel top is connected to the drain. The channel bottom is connected to the source. The channel is vertical and perpendicular to the substrate surface. A first gate stack interfaces with the first channel side and a second gate stack interfaces with the second channel side. A single external gate connection electrically connects the first gate stack and the second gate stack A gate bias (voltage) applied on the single external gate connection biases the first channel side in accumulation and biases the second channel side in inversion. The first gate stack is made of a first high-k dielectric layer and a first gate metal layer.

Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.