Patents by Inventor Karthik Chandrasekar
Karthik Chandrasekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11494120Abstract: Memory transactions in a computing device may be scheduled by forming subsets of a set of memory transactions corresponding to memory transaction requests directed to a DRAM. Each subset may include transactions identified by the same combination of direction (read or write) and DRAM rank as each other. The transactions selected for inclusion in each subset may be determined based on efficiency. One of the subsets may be selected based on a metric applied to each subset, and the transactions in the selected subset may be sent to the DRAM.Type: GrantFiled: October 2, 2020Date of Patent: November 8, 2022Assignee: QUALCOMM IncorporatedInventors: Vikrant Kumar, Karthik Chandrasekar
-
Patent number: 11444624Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.Type: GrantFiled: October 19, 2020Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Karthik Chandrasekar, Guang Chen, Wendemagegnehu T. Beyene, Ravi Prakash Gutala
-
Publication number: 20220107753Abstract: Memory transactions in a computing device may be scheduled by forming subsets of a set of memory transactions corresponding to memory transaction requests directed to a DRAM. Each subset may include transactions identified by the same combination of direction (read or write) and DRAM rank as each other. The transactions selected for inclusion in each subset may be determined based on efficiency. One of the subsets may be selected based on a metric applied to each subset, and the transactions in the selected subset may be sent to the DRAM.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Inventors: Vikrant KUMAR, Karthik CHANDRASEKAR
-
Patent number: 11227834Abstract: A system including an analog block and a digital block. The analog block and the digital block are arranged on a package. The package includes a first ground coupled to the analog block and a second ground coupled to the digital block. The second ground is physically separate from the first ground. The package also includes a noise-mitigation stitching connector that has a first end connected to the first ground and a second end connected to the second ground.Type: GrantFiled: January 29, 2020Date of Patent: January 18, 2022Assignee: SEAGATE TECHNOLOGY LLCInventors: Karthik Chandrasekar, Ratnakar Dadi, Shawn Tzung-Sheng Lo, Emmanuel Atta, Alexander Tain, Subodh Yashwant Bhike
-
Publication number: 20210233845Abstract: A system including an analog block and a digital block. The analog block and the digital block are arranged on a package. The package includes a first ground coupled to the analog block and a second ground coupled to the digital block. The second ground is physically separate from the first ground. The package also includes a noise-mitigation stitching connector that has a first end connected to the first ground and a second end connected to the second ground.Type: ApplicationFiled: January 29, 2020Publication date: July 29, 2021Inventors: Karthik Chandrasekar, Ratnakar Dadi, Shawn Tzung-Sheng Lo, Emmanuel Atta, Alexander Tain, Subodh Yashwant Bhike
-
Publication number: 20210036705Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.Type: ApplicationFiled: October 19, 2020Publication date: February 4, 2021Inventors: Karthik Chandrasekar, Guang Chen, Wendemagegnehu T. Beyene, Ravi Prakash Gutala
-
Patent number: 10812085Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.Type: GrantFiled: December 27, 2018Date of Patent: October 20, 2020Assignee: Intel CorporationInventors: Karthik Chandrasekar, Guang Chen, Wendemagegnehu T. Beyene, Ravi Prakash Gutala
-
Patent number: 10770443Abstract: An integrated circuit device that may include programmable logic fabric disposed on an integrated circuit die and a base die that may include clocking circuitry. Synchronization between logic resources in the programmable logic fabric may be performed using clock signals received from the clocking circuitry. The clocking circuitry in the base die may include phase-locked loops, delay-locked loops, clock trees, and other similar circuitry.Type: GrantFiled: September 28, 2018Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Karthik Chandrasekar, Shreepad Panth, Ravi Prakash Gutala
-
Publication number: 20200105732Abstract: An integrated circuit device that may include programmable logic fabric disposed on an integrated circuit die and a base die that may include clocking circuitry. Synchronization between logic resources in the programmable logic fabric may be performed using clock signals received from the clocking circuitry. The clocking circuitry in the base die may include phase-locked loops, delay-locked loops, clock trees, and other similar circuitry.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Karthik Chandrasekar, Shreepad Panth, Ravi Prakash Gutala
-
Patent number: 10504819Abstract: An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface of the integrated circuit die. The cooling structure includes a group of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant. The cooling channel includes first and second sub-channels. The first sub-channel has a first size that allows a higher flow rate of the coolant to cool the first circuit region. The second sub-channel has a second size that allows a lower flow rate of the coolant to cool the second circuit region.Type: GrantFiled: November 11, 2015Date of Patent: December 10, 2019Assignee: Altera CorporationInventors: Ravi Gutala, Arifur Rahman, Karthik Chandrasekar
-
Publication number: 20190131976Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.Type: ApplicationFiled: December 27, 2018Publication date: May 2, 2019Inventors: Karthik Chandrasekar, Guang Chen, Wendemagegnehu T. Beyene, Ravi Prakash Gutala
-
Patent number: 10020267Abstract: A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.Type: GrantFiled: January 23, 2017Date of Patent: July 10, 2018Assignee: Altera CorporationInventors: Arifur Rahman, Karthik Chandrasekar
-
Publication number: 20180102776Abstract: A multichip package is provided that includes multiple integrated circuit (IC) dies mounted on a shared interposer. The IC dies may communicate with one another via corresponding input-output (IO) elements on the dies. The interposer may include a system-level power management block that is configured to coordinate low-power entry and exit for the IO elements based on customer application needs. Performing application-specific power gating, which may include a combination of coarse-grained and fine-grained power gating control of the IO elements while the IO interface is sitting idle, can help maximize power savings in memory and a variety of other user applications.Type: ApplicationFiled: October 7, 2016Publication date: April 12, 2018Inventors: Karthik Chandrasekar, Chee Hak Teh
-
Patent number: 9935052Abstract: Circuitry having power lines with comparable path resistances may include input-output blocks in an integrated circuit (IC) that are coupled to respective sets of bumps on the IC. The circuitry may have a core region and a periphery region. Groups of input-output blocks may be formed in the periphery region. A first set of power lines in the circuitry extends from the core region to the first group of input-output blocks whereas a second set of power lines in the circuitry extends from the core region to the second group of input-output blocks. The first and second sets of power lines are physically separate from each other.Type: GrantFiled: November 26, 2014Date of Patent: April 3, 2018Assignee: Altera CorporationInventors: Hui Liu, Karthik Chandrasekar, Kyung Suk Oh, Kaushik Chanda, Arifur Rahman
-
Publication number: 20170133329Abstract: A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.Type: ApplicationFiled: January 23, 2017Publication date: May 11, 2017Applicant: Altera CorporationInventors: Arifur Rahman, Karthik Chandrasekar
-
Publication number: 20170133298Abstract: An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface of the integrated circuit die. The cooling structure includes a group of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant. The cooling channel includes first and second sub-channels. The first sub-channel has a first size that allows a higher flow rate of the coolant to cool the first circuit region. The second sub-channel has a second size that allows a lower flow rate of the coolant to cool the second circuit region.Type: ApplicationFiled: November 11, 2015Publication date: May 11, 2017Applicant: Altera CorporationInventors: Ravi Gutala, Arifur Rahman, Karthik Chandrasekar
-
Patent number: 9583431Abstract: A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.Type: GrantFiled: November 11, 2014Date of Patent: February 28, 2017Assignee: Altera CorporationInventors: Arifur Rahman, Karthik Chandrasekar
-
Patent number: 9129935Abstract: A multi-chip package that includes multiple integrated circuits is provided. An integrated circuit in the multi-chip package may be mounted on an interposer. The interposer may be mounted on a package substrate. The integrated circuit may have internal power supply terminals coupled to on-package decoupling (OPD) capacitor circuitry that are formed as part of the package substrate. The power supply terminals on the integrated circuit may be coupled to conductive routing paths and through-silicon vias (TSVs) in the interposer via microbumps. The through-silicon vias in the interposer may be coupled to the OPD capacitor circuitry via flip-chip bumps. The conductive routing paths and the TSVs in the interposer may be coupled to the internal integrated circuit power supply terminals in a way that minimizes power supply resonance noise.Type: GrantFiled: October 5, 2012Date of Patent: September 8, 2015Assignee: Altera CorporationInventors: Karthik Chandrasekar, Arifur Rahman, Jeffrey Tyhach