Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract: Techniques are disclosed for partitioning a placement of a circuit design into a plurality of regions. A constraint is generated based on the partitioning of the placement and on the sequential elements that are located within each region. The constraint is provided to one or more design tools, and the constraint forces sequential elements to fall within the same region on the next placement. Some regions can be classified as guides, and these regions act as a recommendation for a design tool instead of as an explicit rule. Other regions can be classified as inclusive, and sequential elements can be allowed to enter the region but any sequential elements already in the region must stay in the region. Further regions can be classified as exclusive, and no sequential elements may enter or leave these regions on the next placement of the circuit design.

Abstract: A computer-implemented method for determining resources utilized by a service request in a data processing system. The method includes determining monitored relationship types from monitoring data, determining relationship domains, determining intra-domain relationships from relationships that are internal to the relationship domains and determining cross-domain relationships from the intra-domain relationships that are linked between pairs of the relationship domains, and determining resources utilized by the service request from the intra-domain and cross-domain relationships. The domains are derived from one of the relationship types that is monitored by a single monitoring application.

Abstract: An integrated circuit (IC) includes a functional circuit and a capacitor cell. The functional circuit may operate with one of two power supply voltages. The capacitor cell is used to provide power supply decoupling for the functional circuit, and includes multiple capacitors, each designed to withstand a maximum voltage equal to the lower of the two power supply voltages. When the functional circuit is to operate with the higher of the two power supply voltages, the capacitors in the capacitor cell are coupled in a series arrangement between power supply and ground terminals of the IC. When the functional circuit is to operate with the lower of the two power supply voltages, the capacitors in the capacitor cell are coupled in a parallel arrangement between the power supply and ground terminals. In an embodiment, the functional circuit is an input-output (I/O) circuit powered by 1.8V or 3.3V power supplies.

Abstract: An integrated circuit (IC) includes a functional circuit and a capacitor cell. The functional circuit may operate with one of two power supply voltages. The capacitor cell is used to provide power supply decoupling for the functional circuit, and includes multiple capacitors, each designed to withstand a maximum voltage equal to the lower of the two power supply voltages. When the functional circuit is to operate with the higher of the two power supply voltages, the capacitors in the capacitor cell are coupled in a series arrangement between power supply and ground terminals of the IC. When the functional circuit is to operate with the lower of the two power supply voltages, the capacitors in the capacitor cell are coupled in a parallel arrangement between the power supply and ground terminals. In an embodiment, the functional circuit is an input-output (I/O) circuit powered by 1.8V or 3.3V power supplies.

Abstract: The method, system, and apparatus of on-die Thevenin termination for high speed I/O interface are disclosed. In one embodiment, a system of terminating a transmission line of a chip includes a pull-up circuit located within the chip comprising a voltage source and a positive switch device coupled with the transmission line of the chip, a pull-down circuit located within the chip comprising a ground and a negative switch device coupled with the transmission line of the chip, a resistor located within the chip coupled with the voltage source, the positive switch device, the ground, the negative switch device, and a pad coupled with the resistor to terminate the transmission line of the chip. The system may include resistors coupled in parallel with each other. The system may include an impedance module to determine a load impedance value as seen from the pad that matches a source impedance value.

Abstract: An aspect of the present invention provides an input block which can receive input signals of a higher voltage swing when the internal components are fabricated using a lower voltage process. In an embodiment, the input block is designed to prevent current flow into an input signal path when the input signal is at a logic low level. In another embodiment, the input block is designed to recognize a logic value corresponding to a logic high level of input signals at a higher voltage level during a transition from logic low to logic high.

Abstract: An output block fabricated using a lower-voltage process provides output signals with a higher voltage swing. The output block contains a differential amplifier portion and a hold circuit portion. The differential amplifier portion is activated only when the logic level of an output signal needs to be switched. Once the logic level is switched, the hold circuit portion maintains the logic level. As a result, high switching speeds may be achieved with relatively low power consumption. The circuits of the output block are also designed so that no constituent components are subjected to excessive voltages, thereby providing enhanced reliability.

Abstract: A computer-implemented method for determining resources utilized by a service request in a data processing system. The method includes determining monitored relationship types from monitoring data, determining relationship domains, determining intra-domain relationships from relationships that are internal to the relationship domains and determining cross-domain relationships from the intra-domain relationships that are linked between pairs of the relationship domains, and determining resources utilized by the service request from the intra-domain and cross-domain relationships. The domains are derived from one of the relationship types that is monitored by a single monitoring application.

Abstract: An aspect of the present invention minimizes static current consumption in an output block which receives a lower strength input signal and drives a corresponding output signal with a higher strength. Such a feature may be obtained while ensuring that no closed path exists between a first and second reference potentials (having voltage levels equaling upper and lower limits of the swing of the output signal) used by a circuit portion driving a pair of transistors operating as an inverter in the output block. In one embodiment, such a closed path is avoided during the steady state of the output signal, while in an alternative embodiment, the closed path is avoided during the transitions as well.

Abstract: Reducing the effect of coupling on a reference voltage received at a node of an output buffer, wherein the effect of coupling is due to the transitions in the output signals. An inverted signal of the output signal is connected to the node through an impedance (e.g., capacitor) that stores energy. The inverted signal pulls the node in the opposite voltage level direction compared to the coupling effect of the output signal, thereby leaving the reference voltage substantially unchanged. By selecting the capacitance of the capacitor equaling the parasitic capacitance between the node and the output of the output buffer, coupling may be reduced substantially.