Patents by Inventor Karthik Ramu
Karthik Ramu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947487Abstract: Methods and systems are disclosed for performing dataflow execution by an accelerated processing unit (APU). Techniques disclosed include decoding information from one or more dataflow instructions. The decoded information is associated with dataflow execution of a computational task. Techniques disclosed further include configuring, based on the decoded information, dataflow circuitry, and, then, executing the dataflow execution of the computational task using the dataflow circuitry.Type: GrantFiled: June 28, 2022Date of Patent: April 2, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Johnathan Robert Alsop, Karthik Ramu Sangaiah, Anthony T. Gutierrez
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Publication number: 20230418782Abstract: Methods and systems are disclosed for performing dataflow execution by an accelerated processing unit (APU). Techniques disclosed include decoding information from one or more dataflow instructions. The decoded information is associated with dataflow execution of a computational task. Techniques disclosed further include configuring, based on the decoded information, dataflow circuitry, and, then, executing the dataflow execution of the computational task using the dataflow circuitry.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Johnathan Robert Alsop, Karthik Ramu Sangaiah, Anthony T. Gutierrez
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Publication number: 20230409336Abstract: In accordance with described techniques for VLIW Dynamic Communication, an instruction that causes dynamic communication of data to at least one processing element of a very long instruction word (VLIW) machine is dispatched to a plurality of processing elements of the VLIW machine. A first count of data communications issued by the plurality of processing elements and a second count of data communications served by the plurality of processing elements are maintained. At least one additional instruction is determined for dispatch to the plurality of processing elements of the VLIW machine based on the first count and the second count. For example, an instruction that is independent of the instruction is determined for dispatch while the first count and the second count are unequal, and an instruction that is dependent on the instruction is determined for dispatch based on the first count and the second count being equal.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Sriseshan Srikanth, Karthik Ramu Sangaiah, Anthony Thomas Gutierrez, Vedula Venkata Srikant Bharadwaj, John Kalamatianos
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Patent number: 11816490Abstract: VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very long instruction word machine and operations for execution by the very long instruction word machine is obtained. A power setting of the very long instruction word machine is adjusted based on the power configuration of the instruction, and the operations of the instruction are executed by the very long instruction word machine.Type: GrantFiled: December 14, 2021Date of Patent: November 14, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Anthony Thomas Gutierrez, Karthik Ramu Sangaiah, Vedula Venkata Srikant Bharadwaj
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Patent number: 11797410Abstract: A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of processor cores are to be configured at a given performance level, the one or more selected chiplets having been selected based on the chiplet-level performance information and performance requirements. The controller configures the specified number of processor cores of the one or more selected chiplets at the given performance level. A task is then run on the specified number of processor cores of the one or more selected chiplets at the given performance level.Type: GrantFiled: November 15, 2021Date of Patent: October 24, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Shrikanth Ganapathy, Yasuko Eckert, Anthony Gutierrez, Karthik Ramu Sangaiah, Vedula Venkata Srikant Bharadwaj
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Publication number: 20230185575Abstract: VLIW directed Power Management is described. In accordance with described techniques, a program is compiled to generate instructions for execution by a very long instruction word machine. During the compiling, power configurations for the very long instruction word machine to execute the instructions are determined, and fields of the instructions are populated with the power configurations. In one or more implementations, an instruction that includes a power configuration for the very long instruction word machine and operations for execution by the very long instruction word machine is obtained. A power setting of the very long instruction word machine is adjusted based on the power configuration of the instruction, and the operations of the instruction are executed by the very long instruction word machine.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Anthony Thomas Gutierrez, Karthik Ramu Sangaiah, Vedula Venkata Srikant Bharadwaj
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Publication number: 20230153218Abstract: A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of processor cores are to be configured at a given performance level, the one or more selected chiplets having been selected based on the chiplet-level performance information and performance requirements. The controller configures the specified number of processor cores of the one or more selected chiplets at the given performance level. A task is then run on the specified number of processor cores of the one or more selected chiplets at the given performance level.Type: ApplicationFiled: November 15, 2021Publication date: May 18, 2023Inventors: Shrikanth Ganapathy, Yasuko Eckert, Anthony Gutierrez, Karthik Ramu Sangaiah, Vedula Venkata Srikant Bharadwaj
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Publication number: 20110173359Abstract: A computer-implemented device provides security events from publishers to subscribers. There is provided a message bus, configured to contain a plurality of security events. Also provided is a receiver unit, responsive to a plurality of publishers, to receive the plurality of security events from the publishers. There is also a queue unit, responsive to receipt of the security events, to queue the plurality of security events in the message bus. Also, there is a transport unit, responsive to the security events in the message bus, to transport the plurality of security events in the message bus to a plurality of subscribers.Type: ApplicationFiled: March 1, 2011Publication date: July 14, 2011Applicant: Novell, Inc.Inventors: Dipto CHAKRAVARTY, Usman Choudhary, Ofer Zajicek, Srinivasa Phanindra Mallapragada, John Paul Gassner, Frank Anthony Pellegrino, John Melvin Antony, Tao Yu, Michael Howard Cooper, William Matthew Weiner, Magdalence Ramona Merritt, Peng Liu, Raghunath Boyalakuntla, Srivani Sangita, Vasile Adiaconitei, Shahid Saied Malik, Karthik Ramu, Prathap Adusumilli, Walter Mathews, Adedoyin Akinnurun, Brett Hankins
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Patent number: 7926099Abstract: A computer-implemented device provides security events from publishers to subscribers. There is provided a message bus, configured to contain a plurality of security events. Also provided is a receiver unit, responsive to a plurality of publishers, to receive the plurality of security events from the publishers. There is also a queue unit, responsive to receipt of the security events, to queue the plurality of security events in the message bus. Also, there is a transport unit, responsive to the security events in the message bus, to transport the plurality of security events in the message bus to a plurality of subscribers.Type: GrantFiled: December 27, 2005Date of Patent: April 12, 2011Assignee: Novell, Inc.Inventors: Dipto Chakravarty, Usman Choudhary, Ofer Zajicek, Srinivasa Phanindra Mallapragada, John Paul Gassner, Frank Anthony Pellegrino, John Melvin Antony, Tao Yu, Michael Howard Cooper, William Matthew Weiner, Magdalene Ramona Merritt, Peng Liu, Raghunath Boyalakuntla, Srivani Sangita, Vasile Adiaconitei, Shahid Saied Malik, Karthik Ramu, Prathap Adusumilli, Walter Mathews, Adedoyin Akinnurun, Brett Hankins