Patents by Inventor Karthika PERIYATHAMBI

Karthika PERIYATHAMBI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10331410
    Abstract: A true random number generator (TRNG) uses an analog circuit with a ring oscillator configured to collapse from an unstable oscillation state to a stable oscillation state at a random collapse time and counter counting a counter value representing the random collapse time. Various techniques are used to harden the TRNG including a truncator generating a true random number based on a truncation of the reference count value and a dedicated voltage regulator supplying power to the analog core including the ring oscillator. Techniques also include various solutions for drawing a constant current such as using a Gray code counter and adding noise current during and/or after the collapse event with a dummy inverter chain. Bit churning, bit obfuscation entropy enhancers and various post processing techniques may be employed to further harden the TRNG. An attack detection module may raise alerts when the TRNG is being attacked.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 25, 2019
    Assignee: Google LLC
    Inventors: William Wesson, Scott Johnson, Karthika Periyathambi, Lynn Bos
  • Publication number: 20180129476
    Abstract: A true random number generator (TRNG) uses an analog circuit with a ring oscillator configured to collapse from an unstable oscillation state to a stable oscillation state at a random collapse time and counter counting a counter value representing the random collapse time. Various techniques are used to harden the TRNG including a truncator generating a true random number based on a truncation of the reference count value and a dedicated voltage regulator supplying power to the analog core including the ring oscillator. Techniques also include various solutions for drawing a constant current such as using a Gray code counter and adding noise current during and/or after the collapse event with a dummy inverter chain. Bit churning, bit obfuscation entropy enhancers and various post processing techniques may be employed to further harden the TRNG. An attack detection module may raise alerts when the TRNG is being attacked.
    Type: Application
    Filed: November 9, 2016
    Publication date: May 10, 2018
    Applicant: Google Inc.
    Inventors: William WESSON, Scott JOHNSON, Karthika PERIYATHAMBI, Lynn BOS