Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate having at least two different dielectric layers with different dielectric materials and methods for fabricating the same. One example embedded trace substrate generally includes a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; and a second metal layer disposed below the second dielectric layer.

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate having at least two different dielectric layers with different dielectric materials and methods for fabricating the same. One example embedded trace substrate generally includes a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; and a second metal layer disposed below the second dielectric layer.

Abstract: Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising one or more metal pads, wherein the processing may comprise: forming a second metal contact on the one or more metal pads; forming a pillar on the second metal contact, and forming a solder bump on the second metal contact and the pillar, wherein the pillar extends into the solder bump. The second metal contact may comprise a stepped mushroom shaped bump, a sloped mushroom shaped bump, a cylindrical post, and/or a redistribution layer. The semiconductor wafer may comprise silicon. A solder brace layer may be formed around the second metal contact. The second metal contact may be tapered down to a smaller area at the one or more metal pads on the semiconductor wafer. A seed layer may be formed between the second metal contact and the one or more metal pads on the semiconductor wafer. The pillar may comprise copper.

Abstract: Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising one or more metal pads, wherein the processing may comprise: forming a second metal contact on the one or more metal pads; forming a pillar on the second metal contact, and forming a solder bump on the second metal contact and the pillar, wherein the pillar extends into the solder bump. The second metal contact may comprise a stepped mushroom shaped bump, a sloped mushroom shaped bump, a cylindrical post, and/or a redistribution layer. The semiconductor wafer may comprise silicon. A solder brace layer may be formed around the second metal contact. The second metal contact may be tapered down to a smaller area at the one or more metal pads on the semiconductor wafer. A seed layer may be formed between the second metal contact and the one or more metal pads on the semiconductor wafer. The pillar may comprise copper.

Abstract: Systems, methods and/or techniques for mushroom shaped bump on repassivation are described. A method of forming a chip scale package may include applying a first photoresist layer over a semiconductor wafer, developing away a portion of the first photoresist layer to define a cylindrically shaped template with substantially vertical side walls, and plating metal at least partially within the template to form a bump. The bump may include a first cylindrical base portion, a cap, and a lip formed by a portion of the cap that extends horizontally outward beyond the first cylindrical base portion. The cap and lip may be formed such that a vertical distance exists between the lip and the semiconductor wafer, defining an intrusion area. The method may include removing excess portions of the first photoresist layer, including portions residing in the intrusion area, to isolate the bump.