Patents by Inventor Kartik Reddy

Kartik Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11917456
    Abstract: Systems and methods described herein use group segmentation of applications (referred to herein as “slicing classes”), based on common service requirements, to allow carriers to assign UE traffic to network slices. A UE stores slicing class definitions for use with UE Route Selection Policies (URSP). Each of the slicing class definitions include network quality of service (QoS) characteristics that are applicable to network traffic for multiple software applications. The UE maps the software applications to corresponding slicing class identifiers associated with the slicing class definitions. The UE also stores URSP rules for associating a slicing class identifier with a network slice identifier. A UE operating system sends, to a modem, one of the slicing class identifiers for an application that is requesting attachment to a wireless network. The modem sends a registration request with a selected network slice identifier based on the received slicing class identifier and the URSP rules.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: February 27, 2024
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Deepa Jagannatha, Bharadwaj Vemuri, Kartik P. Umamaheswaran, Garima Garg, Balaji L Raghavachari, Kalyani Bogineni, Kristen Sydney Young, Ratul K. Guha, Sudhakar Reddy Patil, Violeta Cakulev
  • Patent number: 8138806
    Abstract: Driver circuit for high voltage differential signaling. The circuit includes a first positive driver that generates a first positive transition at a first output in response to an input. The circuit also includes a first current element coupled to the first positive driver to enable generation of a current. Further, the circuit includes a first negative driver coupled to the first current element, and responsive to the input and the current, due to the first current element, to generate a first negative transition, at a second output, at a rate similar to that of the first positive transition.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: March 20, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jayesh Gangaprasad Wadekar, Sumantra Seth, Kartik Reddy
  • Publication number: 20110175649
    Abstract: Driver circuit for high voltage differential signaling. The circuit includes a first positive driver that generates a first positive transition at a first output in response to an input. The circuit also includes a first current element coupled to the first positive driver to enable generation of a current. Further, the circuit includes a first negative driver coupled to the first current element, and responsive to the input and the current, due to the first current element, to generate a first negative transition, at a second output, at a rate similar to that of the first positive transition.
    Type: Application
    Filed: January 20, 2010
    Publication date: July 21, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Jayesh Gangaprasad WADEKAR, Sumantra Seth, Kartik Reddy