Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of discrete ferroelectric material portions located at levels of the electrically conductive layers. The discrete ferroelectric material portions protrude inward into the memory opening relative to vertical sidewalls of the insulating layers.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and having a lateral undulation in a vertical cross-sectional profile such that the memory opening laterally protrudes outward at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and including a vertical stack of blocking dielectric material portions located at the levels of the electrically conductive layers, a vertical stack of discrete memory elements located at the levels of the electrically conductive layers and including a respective contoured charge storage material portion, a tunneling dielectric layer overlying the contoured inner sidewalls of the tubular charge storage material portion, and a vertical semiconductor channel.

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and composite layers that are interlaced along a vertical direction, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and an inner ferroelectric material layer including a first ferroelectric material, and a vertical stack of electrically-non-insulating material portions located between the inner ferroelectric material layer and the composite layers. Each of the composite layers includes a respective electrically conductive layer and a respective outer ferroelectric material layer including a second ferroelectric material, embedding the respective electrically conductive layer, and contacting a respective electrically-non-insulating material portion.

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each of the electrically conductive layers include a molybdenum layer and a plurality of conductive capping material portions in contact with an outer sidewall of a respective one of the memory opening fill structures.

Abstract: A structure includes semiconductor devices located over a substrate, a first interconnect-level dielectric layer located above the semiconductor devices, a first metal structure embedded in the first interconnect-level dielectric layer, where a top surface of the first metal structure and a top surface of the first interconnect-level dielectric layer are located in a same first horizontal plane, a spacer dielectric material layer having a contoured top surface and a planar bottom surface located in the first horizontal plane on the top surface of the first interconnect-level dielectric layer, at least one opening located in the spacer dielectric material layer, a metal cap structure located in the at least one opening and having a bottom surface in contact with at least a portion of the top surface of the first metal structure, and a second metal structure located on a top surface of the metal cap structure.

Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate; forming an etch mask material layer containing an opening over the alternating stack; performing a first anisotropic etch process that etches unmasked upper portions of the alternating stack to form a via opening below the opening in the etch mask material layer; forming a combination of a non-conformal cladding liner and a conformal sacrificial spacer layer over the etch mask material layer and in peripheral portions of the via opening; performing a punch-through process that etches a horizontally-extending portion of the conformal sacrificial spacer layer from a bottom portion of the via opening; and vertically extending the via opening by performing a second anisotropic etch process that etches unmasked lower portions of the alternating stack selective to the non-conformal cladding liner and the conformal sacrificial spacer layer.

Abstract: A method includes forming an alternating stack of first material layers and second material layers, forming an etch mask material layer containing an opening over the alternating stack, forming a non-conformal cladding liner over the etch mask material layer, where the non-conformal cladding liner includes a horizontally extending portion that overlies a horizontal top surface of the etch mask material layer and a vertically extending portion contacting a sidewall of the opening in the etch mask material layer, implanting ions of dopant atoms into the non-conformal cladding line, and performing an second anisotropic etch process that etches an unmasked portion of the alternating stack selective to the etch mask material layer and the non-conformal cladding liner. The non-conformal cladding liner provides a higher etch resistance relative to the unmasked portion of the alternating stack after the step of implanting ions than before the step of implanting ions.

Abstract: An alternating stack of insulating layers and electrically conductive layers is formed over a substrate, and a memory opening vertically extends through the alternating stack. The memory opening is laterally expanded at levels of the insulating layers. At least one blocking dielectric layer is formed in the memory opening. A first vertical stack of discrete charge storage elements is formed at levels of the electrically conductive layers. A second vertical stack of discrete dielectric material portions is formed at the levels of the insulating layers. A tunneling dielectric layer is formed over the first vertical stack and the second vertical stack. A vertical semiconductor channel is formed on the tunneling dielectric layer.

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a memory material layer having a straight inner cylindrical sidewall that vertically extends through a plurality of electrically conductive layers within the alternating stack without lateral undulation and a laterally-undulating outer sidewall having outward lateral protrusions at levels of the plurality of electrically conductive layers.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film. The memory film includes a contoured blocking dielectric layer including sac-shaped lateral protrusions located at levels of the electrically conductive layers, a tunneling dielectric layer in contact with the vertical semiconductor channel, and a vertical stack of charge storage material portions located within volumes enclosed by the sac-shaped lateral protrusions.