Patents by Inventor Kashyap Desai

Kashyap Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Performance improvements in input/output operations between a host system and an adapter-coupled cache
    Patent number: 9104334
    Abstract: A modified or host driver operable on a host computer communicates with a host interface of a PCIe adapter. A controller memory space is managed by the kernel space of the host operating system. The modified driver entirely avoids the overhead associated with making a copy from the application or user space to a separate kernel space managed by the operating system in the host computer. The modified driver uses a base address register to identify the location of the cache storage in the controller memory space. The size of the cache store is communicated to the modified driver upon a power on initialization of the PCIe adapter and the host computer. A memory map managed by the modified driver identifies cache storage locations as an offset from the base address register.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: August 11, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd
    Inventors: Naresh Madhusudana, Naveen Krishnamurthy, Kashyap Desai
  • Performance Improvements in Input / Output Operations Between a Host System and an Adapter-Coupled Cache
    Publication number: 20150058557
    Abstract: A modified or host driver operable on a host computer communicates with a host interface of a PCIe adapter. A controller memory space is managed by the kernel space of the host operating system. The modified driver entirely avoids the overhead associated with making a copy from the application or user space to a separate kernel space managed by the operating system in the host computer. The modified driver uses a base address register to identify the location of the cache storage in the controller memory space. The size of the cache store is communicated to the modified driver upon a power on initialization of the PCIe adapter and the host computer. A memory map managed by the modified driver identifies cache storage locations as an offset from the base address register.
    Type: Application
    Filed: December 13, 2013
    Publication date: February 26, 2015
    Applicant: LSI Corporation
    Inventors: Naresh Madhusudana, Naveen Krishnamurthy, Kashyap Desai