Patents by Inventor Katherine Cheng

Katherine Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processing core and MRAM memory unit integrated on a single chip
    Patent number: 11968843
    Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
  • Balanced flow dialysis machine
    Patent number: 11931492
    Abstract: A system and method for balancing flows of renal replacement fluid is disclosed. The method uses pressure controls and pressure sensing devices to more precisely meter and balance the flow of fresh dialysate and spent dialysate. The balancing system may use one or two balancing devices, such as a balance tube, a tortuous path, or a balance chamber.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 19, 2024
    Assignees: BAXTER INTERNATIONAL INC., BAXTER HEALTHCARE SA
    Inventors: Michael E. Hogard, Donald D. Busby, Robert W. Childers, Yuanpang Samuel Ding, Katherine M. Holian, Mark E. Jablonski, Thomas D. Kelly, Shincy J. Maliekkal, Rodolfo G. Roger, Donald A. Smith, Atif M. Yardimci, Ying-Cheng Lo
  • Memory device and manufacturing method thereof
    Patent number: 11937426
    Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
  • Display screen or portion thereof with graphical user interface
    Patent number: D895650
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 8, 2020
    Assignee: Halogen Networks, LLC
    Inventors: Samuel Griffith, Katherine Cheng, Anardo Cuello, Stephen Gordon, Jordan David Dunn