Patents by Inventor Katherine Chiang
Katherine Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990169Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes an operative memory device coupled to a bit-line. The operative memory device is configured to store a data state. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus includes one or more regulating MTJ devices that are configured to control a current provided to the operative memory device. The one or more regulating MTJ devices respectively include a free layer, a dielectric barrier layer on the free layer, and a pinned layer separated from the free layer by the dielectric barrier layer. The pinned layer covers a center of a surface of the dielectric barrier layer that faces the pinned layer.Type: GrantFiled: August 3, 2021Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
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Patent number: 11968843Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.Type: GrantFiled: February 7, 2019Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
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Publication number: 20230022057Abstract: Methods for retrieving images from a database are provided. A query image is obtained. A plurality of patches are extracted from the query image. A set of weightings is obtained according to a plurality of bases of a sparsity-based dictionary. The set of weightings includes a plurality of non-zero weightings. The patches are encoded with the set of weightings to obtain an encoding matrix. The database is searched based on the encoding matrix to retrieve the images corresponding to the query image. The database and the dictionary are dynamically updated to adapt to the query image encountered.Type: ApplicationFiled: July 16, 2021Publication date: January 26, 2023Inventor: Katherine CHIANG
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Publication number: 20210366529Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes an operative memory device coupled to a bit-line. The operative memory device is configured to store a data state. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus includes one or more regulating MTJ devices that are configured to control a current provided to the operative memory device. The one or more regulating MTJ devices respectively include a free layer, a dielectric barrier layer on the free layer, and a pinned layer separated from the free layer by the dielectric barrier layer. The pinned layer covers a center of a surface of the dielectric barrier layer that faces the pinned layer.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
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Patent number: 11133044Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes a first memory device and a second memory device arranged over a substrate. The first memory device is coupled to a first bit-line. The second memory device is coupled to a second bit-line. A shared control element is arranged within the substrate and is configured to provide access to the first memory device and to separately provide access to the second memory device. The shared control element includes one or more control devices sharing one or more components.Type: GrantFiled: June 1, 2018Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Katherine Chiang, Chung-Te Lin, Min Cao, Randy Osborne
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Patent number: 11094361Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has an operative magnetic tunnel junction (MTJ) device configured to store a data state. The operative MTJ device is coupled to a bit-line. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus has one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device.Type: GrantFiled: September 5, 2018Date of Patent: August 17, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
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Patent number: 10860769Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.Type: GrantFiled: December 19, 2019Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
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Patent number: 10839879Abstract: The present application relates to a memory device. The memory device includes a magnetic tunnel junction (MTJ) current path, a reference current path in parallel with the MTJ current path, and a bias current path in parallel with the MTJ current path and the reference current path. The MTJ current path includes a MTJ memory cell configured to switch between a first data state and a second data state. The reference current path includes a reference memory cell. The bias current path is configured to bias the MTJ current path and the reference current path during read operations so the MTJ current path and the reference current path each carry a current level when the first state is read from the MTJ memory cell and each carry the current level when the second state is read from the MTJ memory cell.Type: GrantFiled: October 24, 2018Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gaurav Gupta, Chung-Te Lin, Katherine Chiang
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Publication number: 20200125782Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
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Publication number: 20200105327Abstract: In some embodiments, the present application provides a memory device. The memory device includes a magnetic tunnel junction (MTJ) current path, a reference current path in parallel with the MTJ current path, and a bias current path in parallel with the MTJ current path and the reference current path. The MTJ current path includes a MTJ memory cell configured to switch between a first data state and a second data state. The reference current path includes a reference memory cell. The bias current path is configured to bias the MTJ current path and the reference current path during read operations so the MTJ current path and the reference current path each carry a current level when the first state is read from the MTJ memory cell and each carry the current level when the second state is read from the MTJ memory cell.Type: ApplicationFiled: October 24, 2018Publication date: April 2, 2020Inventors: Gaurav Gupta, Chung-Te Lin, Katherine Chiang
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Publication number: 20200075074Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has an operative magnetic tunnel junction (MTJ) device configured to store a data state. The operative MTJ device is coupled to a bit-line. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus has one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device.Type: ApplicationFiled: September 5, 2018Publication date: March 5, 2020Inventors: Katherine Chiang, Chung Te Lin, Min Cao, Yuh-Jier Mii, Sheng-Chih Lai
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Publication number: 20200006423Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.Type: ApplicationFiled: February 7, 2019Publication date: January 2, 2020Inventors: Chung-Te Lin, Yen-Chung Ho, Pin-Cheng Hsu, Han-Ting Tsai, Katherine Chiang
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Patent number: 10521538Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.Type: GrantFiled: October 26, 2016Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
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Publication number: 20190371383Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes a first memory device and a second memory device arranged over a substrate. The first memory device is coupled to a first bit-line. The second memory device is coupled to a second bit-line. A shared control element is arranged within the substrate and is configured to provide access to the first memory device and to separately provide access to the second memory device. The shared control element includes one or more control devices sharing one or more components.Type: ApplicationFiled: June 1, 2018Publication date: December 5, 2019Inventors: Katherine Chiang, Chung-Te Lin, Min Cao, Randy Osborne
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Publication number: 20170316138Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.Type: ApplicationFiled: October 26, 2016Publication date: November 2, 2017Inventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
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Publication number: 20040077294Abstract: A system and method are described for manufacturing a lapping plate. In one example, the lapping plate is made by covering a Tin-Antimony plate with photoresist and exposing the resulting photoresist layer with UV light through a wire mesh mask. After development, the non-etch areas can serve as land areas for diamond charging. Such a method may lead to fewer artifacts on the lapping plate and smaller diamond particle dimensions resulting in better processing of read/write heads, especially GMR heads.Type: ApplicationFiled: October 10, 2003Publication date: April 22, 2004Inventors: Niraj Mahadev, Nelson Truong, Winston Jose, Katherine Chiang