Abstract: A system and method for efficiently designing a through silicon via (TSV) macro blocks are described. In various implementations, the circuitry of a processor executes instructions of a place and route tool that provides automatic placement of macro blocks and standard cells on an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library that includes a variety of standard cells and macro blocks. The processor places two functional macros in the floorplan with a channel between them. In the channel, the processor places a TSV macro that includes at least one boundary cell inside of the TSV macro. The processor prevents placement of a boundary cell adjacent to at least one side of the TSV macro despite empty space exists due to no standard cells or macros about the at least one side.

Abstract: An integrated circuit memory is disclosed in which an array of 8 T SRAM cells is arranged in rows and columns using a plurality of write wordlines for each row of 8 T SRAM cells to control write access to cells in the row associated with a first parity/ECC word and a second write wordline operable to control write access to cells in the row associated with a second parity/ECC word.