Abstract: A first logic inversion unit generates an input inversion signal and a buffer unit generates a signal having a same logic as that of the input inversion signal. The first logic inversion unit includes first and second MOS transistors. The first and second MOS transistors have conductivity types different from each other. The buffer unit includes third to sixth MOS transistors. The third and fourth MOS transistors are connected in cascade between a third reference potential and an output node of the buffer unit and have conductivity types different from each other. The fifth and sixth MOS transistors are connected in cascade between the output node of the buffer unit and a fourth reference potential and have conductivity types different from each other.

Abstract: A signal transmission circuit includes an input node through which an input rectangular waveform is supplied, an inverter that generates an inverted input signal, a push-pull circuit that generates an output signal of the signal transmission circuit, a first drive circuit that generates a first drive signal for the push-pull circuit from the inverted input signal and a first adjusted waveform, and a second drive circuit that generates a second drive signal for the push-pull circuit from the inverted input signal and a second adjusted waveform. The first adjusted waveform falls with a first time constant when the input rectangular waveform is high and the second adjusted waveform rises with a second time constant when the input rectangular waveform is low. The output signal of the signal transmission circuit has a rise time correlated to the first adjusted waveform and a fall time correlated to the second adjusted waveform.

Abstract: A high frequency filter includes: an input terminal; an output terminal; and a variable capacitance circuit provided between the input terminal and the output terminal or between a ground and one of the input terminal and the output terminal, and formed on the semiconductor substrate including a capacitor and a switch element. The switch element is connected in series with the capacitor.

Abstract: A high frequency switching circuit is disclosed. The high frequency switching circuit is provided with first and second high frequency signal terminals, a control terminal, a field-effect transistor having a drain, a source and a gate. The field-effect transistor is connected between the first and the second high frequency signal terminals so as to switch a high frequency signal. The high frequency switching circuit is further provided with a variable resistance circuit which is connected between the gate of the field-effect transistor and the control terminal.

Abstract: A switching circuit is disclosed. The switching circuit is provided with first and second signal terminals, a control terminal, first and second resisters, and a field-effect transistor having a drain, a source, a gate and a back-gate. One end of the first resister is connected with the control terminal. The field-effect transistor is connected between the first and second signal terminals. The gate of the field-effect transistor is connected with the other end of the first resister. The back-gate of the field-effect transistor is connected with one end of the second resister. One of the source and drain of the first field-effect transistor is connected with the other end of the second resister.

Abstract: A high frequency switching circuit is disclosed. The high frequency switching circuit is provided with first and second high frequency signal terminals, a control terminal, a field-effect transistor having a drain, a source and a gate. The field-effect transistor is connected between the first and the second high frequency signal terminals so as to switch a high frequency signal. The high frequency switching circuit is further provided with a variable resistance circuit which is connected between the gate of the field-effect transistor and the control terminal.

Abstract: A high frequency switching device includes a control terminal, a power source terminal, a GND terminal, an RF terminal, a switch section, a control section, and protecting diodes. The switch section switches input/output routes of an RF signal input from the RF terminal. The control section controls the switching section, and is connected to the control terminal and the power source terminal. The protecting diodes are provided between the control terminal and the RF terminal, between the control terminal and the GND terminal, and between the power source terminal and the GND terminal.

Abstract: A high frequency switching device includes a control terminal, a power source terminal, a GND terminal, an RF terminal, a switch section, a control section, and protecting diodes. The switch section switches input/output routes of an RF signal input from the RF terminal. The control section controls the switching section, and is connected to the control terminal and the power source terminal. The protecting diodes are provided between the control terminal and the RF terminal, between the control terminal and the GND terminal, and between the power source terminal and the GND terminal.

Abstract: In order to minimize the chip area and improve the linear characteristics obtained when large signals are inputted, a high frequency switch device comprises first, second and third terminals (3, 4, 6); a first circuit composed of a first FET (11), and a first inductor (21) and a first capacitor (25) both connected with the first FET (11) in parallel to each other, one end of the first circuit being connected to the first terminal (3); and a second circuit composed of a second FET (12), and a second inductor (22) and a second capacitor (26) both connected with the second FET (12) in parallel to each other, one end of the second circuit being connected to the first circuit and the other end of the second circuit being connected to the second terminal (4).

Abstract: A switching circuit is made by serially connecting two field effect transistors in series in a small-signal transmission path, each of the transistors being applied with a substantially equal voltage, so as to lower a voltage applied to each of the FETs in the OFF state by voltage division, with the result that a high withstand voltage of the transmission path can be attained and a linear output can be obtained even when a large electric power is transmitted.

Abstract: A standard cell type gallium arsenide logic integrated circuit device includes arrays of standard cells connected to each other on a chip substrate. Each of the standard cells includes a plurality of gallium arsenide logic gates of previously selected type such as NOR gates and an inverter. The logic gate has a direct-coupled type FET logic circuit structure. In each of the standard cells, level-shift circuits are provided only for inputs of those logic gates which are directly connected to connection terminals directly associated with the other standard cell. The level-shift circuits enhance the swing width of a logic signal transmitted between the standard cells which are associated with one another, thereby increasing the operation margin. Such a level-shift circuit is not provided for internal interconnection wirings between the logic gates inside the standard cell.

Abstract: A GaAs (gallium arsenide) semiconductor memory device includes a plurality of memory cells connected in a matrix form by employing a plurality of bit lines and of word lines, and of word line drivers. The memory device is operable under a single power supply. Transfer gates of the memory cells are normally-on type GaAs metal-semiconductor field effect transistors (MESFET's). A parallel circuit including a Schottky diode and a switching GaAs-MESFET is interposed between commonly-connected sources of driver MESFET's of each of the memory cells and the ground line, so that a higher potential of the commonly-connected sources is clamped due to the clamping effect of the Schottky diode when the switching GaAs-MESFET is turned off.

Abstract: A gallium arsenide NAND gate is connected between a power source and a ground potential. The gate is comprised of a load transistor of a normally-on type field effect transistor having an output terminal and a drain connected to the power source, a first driver transistor of a normally-off type field effect transistor having a gate electrode as a first input terminal and a source-to-drain current path series-connected to that of the load transistor, and a second driver transistor of two normally-off type field effect transistors having a common gate electrode for a second input terminal and source-to-drain current paths series-connected between the power source and the ground potential through the series-connected first driver transistor and load transistor. The normally-off type field effect transistors are parallel-connected to each other so as to equally constitute a single driver transistor as the second driver transistor.