Patents by Inventor Katsufusa Shono

Katsufusa Shono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7209885
    Abstract: A compressed-code generating method that is used for compressing information on characters including numerical data, sound and images, and a compressed-code expanding method that is used for restoring and expanding the compressed code generated by using the compressed-code generating method to the original information. Bit strings {y}1 and {y}2 are obtained respectively from a bit string {y} of information to be compressed. A reversible loop that exists in chaos is operated to these obtained bit strings, thereby to execute a reversible compression/expansion of the information using the chaos.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: April 24, 2007
    Assignee: Yazaki Corporation
    Inventors: Katsufusa Shono, Takahiro Abe
  • Patent number: 7054446
    Abstract: Each of plural CPUs enciphers a plaintext code which is a secrecy object according to chaos block encryption and then enciphers it according to chaos stream encryption. Then, it transmits an obtained cipher code through communication line. On the other hand, each of plural CPUs that received the cipher code synchronously restores the received cipher code according to chaos stream encryption and then restores according to chaos block encryption thereby to obtain an original plaintext code.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: May 30, 2006
    Assignee: YAZAKI Corporation
    Inventors: Tetsuya Ishihara, Takahiro Abe, Katsufusa Shono
  • Patent number: 6788787
    Abstract: A chaos-generating loop includes a one dimensional mapping circuit (13) with non-linear input-output characteristics for generating chaos, a linear or non-linear AD converter (15) for converting an analog output of the one dimensional mapping circuit (13) to digital form, a sample-and-hold circuit (17) for holding and outputting the digitally converted value from the AD converter (15), in response to an external clock (C), and a linear or non-linear DA converter (19) for converting an output of the sample-and-hold circuit (17) to analog form and outputting this analog signal to the one dimensional mapping circuit (13), and a decoder for outputting a chaos stream in response to the output of the sample-and-hold circuit (17).
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: September 7, 2004
    Assignee: Yazaki Corporation
    Inventors: Katsufusa Shono, Osamu Ueno, Tetsuya Ishihara
  • Patent number: 6473448
    Abstract: Arithmetic operation is started by substituting an initial value x(0) for a logistic mapping x(t+1)=4x(t){1x(t)} which is a symmetrical nonlinear mapping. The resultant value is again input into the logistic mapping x(t+1)=4x(t){(1−x(t)}, based on an feedback x(t)=x(t+1). This operation is repeated to obtain time series x(t)−t. Isomorphic transform and quantization corresponding to the time series x(t)−t is obtained based on y(t)=[{2/&pgr;·arc sin {square root over (0)}x(t))}·2n] while a quantizing resolution n=1 is substituted for y(t)=[{2/&pgr;·arc sin {square root over (0)}x(t)}·2n]. A time series y(t)−t is determined from the obtained isomorphic transform and quantization. A spread spectrum signal having, as a period thereof, binary code sequence y(t) arbitrarily sampled from the time series y(t)−t is generated.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: October 29, 2002
    Assignee: Yazaki Corporation
    Inventors: Katsufusa Shono, Tetsuya Ishihara
  • Publication number: 20020044652
    Abstract: On a transmitter side, an enciphering means enciphers a plaintext code according to stream enciphering method having a feature in selecting the cycle of a PN signal and then a transmitting means transmits the cryptographic code. On the other hand, on a receiver side, a deciphering means restores the cryptographic code enciphered in the above described procedure to an original plaintext code by carrying out exclusive-OR operations again.
    Type: Application
    Filed: April 2, 2001
    Publication date: April 18, 2002
    Inventors: Takahiro Abe, Katsufusa Shono
  • Publication number: 20020009200
    Abstract: Each of plural CPUs enciphers a plaintext code which is a secrecy object according to chaos block encryption and then enciphers it according to chaos stream encryption. Then, it transmits an obtained cipher code through communication line. On the other hand, each of plural CPUs that received the cipher code synchronously restores the received cipher code according to chaos stream encryption and then restores according to chaos block encryption thereby to obtain an original plaintext code.
    Type: Application
    Filed: May 16, 2001
    Publication date: January 24, 2002
    Inventors: Tetsuya Ishihara, Takahiro Abe, Katsufusa Shono