Abstract: An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.

Abstract: This invention offers a manufacturing method which does not cause a reduction in thickness of a silicon substrate or a carbon contamination in forming a transistor having an LDD stricture and silicide layers formed by a salicide technology. After a gate electrode is formed on the silicon substrate through a gate insulation film, an insulation film made of the same material as the gate insulation film is formed on the gate electrode. A first insulation film made of a material different from the material of the gate insulation film and the insulation film on the gate electrode and a second insulation film made of the same material as the material of the gate insulation film and the insulation film on the gate electrode are formed over the silicon substrate. Spacers made of the second insulation film are formed by dry-etching. Then the LDD structure and openings for forming the silicide layers are formed using wet-etching.

Abstract: This invention offers a manufacturing method which does not cause a reduction in thickness of a silicon substrate or a carbon contamination in forming a transistor having an LDD stricture and silicide layers formed by a salicide technology. After a gate electrode is formed on the silicon substrate through a gate insulation film, an insulation film made of the same material as the gate insulation film is formed on the gate electrode. A first insulation film made of a material different from the material of the gate insulation film and the insulation film on the gate electrode and a second insulation film made of the same material as the material of the gate insulation film and the insulation film on the gate electrode are formed over the silicon substrate. Spacers made of the second insulation film are formed by dry-etching. Then the LDD structure and openings for forming the silicide layers are formed using wet-etching.

Abstract: An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.

Abstract: The invention is to obtain a resistor element having high resistance, a low temperature coefficient, and high uniformity of sheet resistance in a wafer. A field oxide film is formed on a semiconductor substrate. On the field oxide film a non-doped silicon film is formed by a LPCVD method. The silicon film is made of an amorphous silicon film or a polysilicon film. BF2+ is ion implanted in this silicon film. Then, either before or after this ion implantation, N2 annealing is performed at low temperature between 650 and 750° C.

Abstract: There is provided a process of dry etching of a double-layer film composed of a polycrystal silicon film and a metal silicide film formed on a base substance with an etching-proof film composed of an inorganic compound as a mask in a state that reaction gas loaded with at least any one of HBr gas, Br.sub.2 gas and BBr.sub.3 gas is activated by plasma discharge, and the temperature of the base substance is maintained at 60.degree. C. or higher. With this, it is possible to aim at improvement of dimensional controllability and selectivity of etching without using flon gas, and further to arrange so that the configuration after etching of an object to be etched does not depend on an area ratio on a wafer of the area of a region where an etching-proof film is formed to the exposed area of the object to be etched.

Abstract: A process for the preparation of a semiconductor device, includes the steps of, (a) foxing a mask including an organic film on a laminated film consisting of a metal silicide layer and a non-single crystalline silicon layer formed over a substrate on which an oxide layer is formed, (b) etching the laminated film under a plasma atmosphere of a mixed gas including a chlorine gas and an oxygen gas by heating the substrate to a temperature of 60.degree. C. or more to fabricate the laminated film into an almost vertical pattern in section, and (c) removing the mask from the laminated film. In this process, the laminated film consisting of a metal silicide layer on which a resist mask is formed, and a polycrystalline silicon layer formed over a substrate, can be given vertical patterning profile edge, and the uniformity of the etching rate in the substrate is enhanced. Further, as a deposition gas is not used in the present process, the occurrence of loose particles is restrained.

Abstract: Plasma etching with hydrogen bromide or bromine as an etching gas allows a precise control in attaining vertical etching or taper etching with a desired taper angle by controlling the temperature of a mass to be etched, which mass is usually a semiconductor wafer.

Abstract: Plasma etching with hydrogen bromide or bromine as an etching gas allows a precise control of attaining vertical etching or taper etching with a desired taper angle by controlling a temperature of a mass to be etched, which mass is a phosphorus-doped n-type polycrystalline silicon, phosphorus-doped single crystalline or phosphorus-doped silicides semiconductor wafer.