Patents by Inventor Katsuhiko Kubota
Katsuhiko Kubota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7463517Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.Type: GrantFiled: October 9, 2007Date of Patent: December 9, 2008Assignee: Renesas Technology Corp.Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Patent number: 7428167Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.Type: GrantFiled: May 9, 2006Date of Patent: September 23, 2008Assignee: Renesas Technology Corp.Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Publication number: 20080037323Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.Type: ApplicationFiled: October 9, 2007Publication date: February 14, 2008Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Patent number: 7289361Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.Type: GrantFiled: May 12, 2006Date of Patent: October 30, 2007Assignee: Renesas Technology Corp.Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Publication number: 20070176921Abstract: To propose an urban landscape with reality as alive as an actual town and provide a system of realizing the urban landscape.Type: ApplicationFiled: January 27, 2006Publication date: August 2, 2007Inventors: Koji Iwasaki, Katsuhiko Kubota
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Publication number: 20060221688Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.Type: ApplicationFiled: May 12, 2006Publication date: October 5, 2006Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Publication number: 20060202274Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.Type: ApplicationFiled: May 9, 2006Publication date: September 14, 2006Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Patent number: 7042764Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.Type: GrantFiled: June 14, 2005Date of Patent: May 9, 2006Assignee: Renesas Technology Corp.Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Publication number: 20050232008Abstract: A semiconductor integrated circuit device is provided on a semiconductor substrate, and includes a plurality of word lines, a plurality of data lines, and a plurality of electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of word lines and to the plurality of data lines. The erasable non-volatile memory cell each includes a MIS transistor having a floating gate having a first level polycrystalline silicon layer, a source, and a drain coupled to the corresponding data line, and a control gate formed of a semiconductor region in the semiconductor substrate, the control gate being coupled to the corresponding word line.Type: ApplicationFiled: June 14, 2005Publication date: October 20, 2005Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Patent number: 6906954Abstract: 0 Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.Type: GrantFiled: April 6, 2004Date of Patent: June 14, 2005Assignee: Renesas Technology Corp.Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Patent number: 6825504Abstract: In order to eliminate the difference in ESD resistance caused by polarities of excessive voltages applied to an external terminal and enhance ESD resistance of a semiconductor integrated circuit device to both the positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.Type: GrantFiled: October 22, 2002Date of Patent: November 30, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroyasu Ishizuka, Kousuke Okuyama, Katsuhiko Kubota
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Publication number: 20040190339Abstract: Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.Type: ApplicationFiled: April 6, 2004Publication date: September 30, 2004Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Patent number: 6771538Abstract: Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.Type: GrantFiled: July 2, 2003Date of Patent: August 3, 2004Assignee: Renesas Technology Corp.Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Publication number: 20040004894Abstract: Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.Type: ApplicationFiled: July 2, 2003Publication date: January 8, 2004Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Patent number: 6614684Abstract: An information retention capability based on a memory cell which includes pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.Type: GrantFiled: January 28, 2000Date of Patent: September 2, 2003Assignee: Hitachi, Ltd.Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Patent number: 6545311Abstract: An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (G03) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.Type: GrantFiled: August 31, 2001Date of Patent: April 8, 2003Assignee: Hitachi, Ltd.Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Publication number: 20030047751Abstract: In order to eliminate the difference in ESD resistance caused by polarities of excessive voltages applied to an external terminal and enhance ESD resistance of a semiconductor integrated circuit device to both the positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.Type: ApplicationFiled: October 22, 2002Publication date: March 13, 2003Inventors: Hiroyasu Ishizuka, Kousuke Okuyama, Katsuhiko Kubota
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Patent number: 6528839Abstract: An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.Type: GrantFiled: August 31, 2001Date of Patent: March 4, 2003Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama
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Patent number: 6469325Abstract: In order to eliminate a difference in ESD resistance caused by the polarities of excessive voltages applied to an external terminal and enhance the ESD resistance of a semiconductor integrated circuit device to both positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.Type: GrantFiled: May 3, 1999Date of Patent: October 22, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroyasu Ishizuka, Kousuke Okuyama, Katsuhiko Kubota
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Publication number: 20020126521Abstract: An information retention capability based on a memory cell which comprises a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.Type: ApplicationFiled: August 31, 2001Publication date: September 12, 2002Inventors: Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama