Abstract: An information display device includes a display that displays information, a communication unit that contactlessly communicates with an information communication medium, a communication control unit including a transceiver and a power converter such that the transceiver receives the display information from the information communication medium through the communication unit and that the power converter converts an electromagnetic wave received by the communication unit into electric power, and a display control unit including a storage, a voltage monitor, and a display driver such that the storage stores the display information received by the transceiver, that the voltage monitor monitors a voltage of electric power supplied from the power converter, and that the display driver updates, based on the display information stored in the storage, the information displayed on the display.

Abstract: A thin film transistor array includes column wirings extending in a first direction, row wirings extending in a second direction, capacitor wirings, and pixels formed in a matrix. Each pixel includes a thin film transistor, a pixel electrode, and a capacitor electrode. The pixels form a rectangular effective region of an M column by N row matrix structure in which N pixels are formed in the first direction and M pixels are formed in the second direction, where M and N are natural numbers, the row wirings each have a length extending across the M pixels formed in the second direction in the effective region, the column wirings each have a length extending across the N/2 pixels formed in the first direction in the effective region, and the capacitor wirings each have a length which extends across the N pixels formed in the first direction in the effective region.

Abstract: A display device that displays image information in response to a digital display signal includes a display panel signal lines and scanning lines which intersect at right angles with each other, and a plurality of display pixels with optical elements arranged near the intersecting points of the signal lines and scanning lines. A signal driver circuit has a plurality of current generation circuits including a drive current generation circuit for generating drive current from a plurality of gradation currents based on the display signal value supplied to each of the scanning lines, a scanning driver circuit for sequentially applying a scanning signal to each of the scanning lines for setting the selection state of each line of each display pixel, and a gradation current generation circuit for generating gradation currents according to each display signal bit at least based on a constant predetermined reference current.

Abstract: Disclosed is a method of manufacturing a semiconductor device including: forming a photothermal conversion layer in a second area where a semiconductor layer is formed other than a first area where line is formed; and heating the semiconductor layer with the photothermal conversion layer by irradiating light on the first area and the second area.

Abstract: A current generation supply circuit which supplies drive currents corresponding to digital signals for a plurality of loads comprising a signal holding circuit which takes in and holds the digital signals, a current generation circuit which generates the drive currents having a ratio of current values corresponding to the values of the digital signals held in the signal holding circuit relative to the reference current supplied from a constant current source and supplied to the loads, and an operational state setting circuit which overlaps in terms of time and sets the operating state in the signal holding circuit and the current generation circuit in order to execute at least a take-in and hold operation of the digital signals in the signal holding circuit and a generation supply operation of the drive currents in the current generation circuit; as well as raises the operating speed of the current generation supply circuit.

Abstract: A shift register circuit includes a plurality of cascade-connected signal holding circuits each of the signal holding circuits includes an input control circuit to which an input signal is applied, and which fetches and holds the input signal, an output control circuit to which a first control clock signal is applied, and which outputs an output signal corresponding to timings of the held input signal and the first control clock signal, and a reset control circuit to which a reset signal is applied, and which initializes a signal level of the input signal held in the input control circuit. A timing at which the output signal is terminated is set to be ahead of an application start timing of the reset signal.

Abstract: A shift register circuit includes plural stages of signal holding circuits which are cascade-connected to hold a signal based on a supplied input signal, to output an output signal based on the held signal, and to supply the output signal as an input signal to a subsequent stage. Each of the plural stages of signal holding circuits includes an output circuit which is supplied with two types of clock signals consisting of a first clock signal and a second clock signal. A timing of the second clock signal is delayed by a predetermined delay time with respect to a timing of applying the input signal, which is supplied with a signal at a timing delayed by the delay time of the second clock signal from the timing of applying the input signal, and which outputs the output signal at a timing responsive to the first clock signal.

Abstract: An optical sensor includes a photoelectric converter to receive external light and to output a photocurrent signal according to the illuminance of the external light. A current-to-voltage converter converts the photocurrent signal output from the photoelectric converter to a voltage signal. A voltage amplifier amplifies the voltage signal. A current amplifier outputs a current signal corresponding to the voltage signal amplified by the voltage amplifier. Each of the photoelectric converter, current-to-voltage converter, voltage amplifier and current amplifier includes at least one thin-film transistor.

Abstract: A current generation supply circuit which supplies drive currents corresponding to digital signals for a plurality of loads comprising a current generation circuit which supplies output currents to the loads as the drive currents comprising a reference voltage generation circuit in which reference current having a constant current value is supplied and generates reference voltages based on the reference current; a drive current generation circuit which generates the output currents having current value ratios corresponding to the digital signals relative to the reference current based on the reference voltages; and a characteristic control circuit which sets the ratio of the output currents relative to the reference current.

Abstract: An optical sensor includes a photoelectric converter to receive external light and to output a photocurrent signal according to the illuminance of the external light. A current-to-voltage converter converts the photocurrent signal output from the photoelectric converter to a voltage signal. A voltage amplifier amplifies the voltage signal. A current amplifier outputs a current signal corresponding to the voltage signal amplified by the voltage amplifier. Each of the photoelectric converter, current-to-voltage converter, voltage amplifier and current amplifier includes at least one thin-film transistor.

Abstract: A shift register circuit includes plural stages of signal holding circuits which are cascade-connected to hold a signal based on a supplied input signal, to output an output signal based on the held signal, and to supply the output signal as an input signal to a subsequent stage. Each of the plural stages of signal holding circuits includes an output circuit which is supplied with two types of clock signals consisting of a first clock signal and a second clock signal. A timing of the second clock signal is delayed by a predetermined delay time with respect to a timing of applying the input signal, which is supplied with a signal at a timing delayed by the delay time of the second clock signal from the timing of applying the input signal, and which outputs the output signal at a timing responsive to the first clock signal.

Abstract: A shift circuit of a shift register includes an output terminal, an input terminal, a reset terminal. A voltage is applied to a first wiring in response to the output signal from the preceding stage shift circuit to the input terminal and in accordance with the predetermined voltage to the first wiring, outputting an externally applied signal to the output terminal. A voltage level of the first wiring is reduced in response to the output signal to the reset terminal by the preceding stage shift circuit. The voltage is applied to the second wiring in response to a change in the level of the voltage applied to the first wiring. The voltage is applied to a second wiring in response to the output signal to the reset terminal by the preceding stage shift circuit. A voltage level of the output signal is reduced in response to the predetermined voltage to the second wiring.

Abstract: A shift register circuit includes a plurality of cascade-connected signal holding circuits each of the signal holding circuits includes an input control circuit to which an input signal is applied, and which fetches and holds the input signal, an output control circuit to which a first control clock signal is applied, and which outputs an output signal corresponding to timings of the held input signal and the first control clock signal, and a reset control circuit to which a reset signal is applied, and which initializes a signal level of the input signal held in the input control circuit. A timing at which the output signal is terminated is set to be ahead of an application start timing of the reset signal.

Abstract: A display device that displays image information in response to a display signal consisting of digital signals includes a display panel comprising a plurality of signal lines (DL) and a plurality of scanning lines (SL) which intersect at right angles with each other, and a plurality of display pixels (EM) sith optical emlem

Abstract: A shift circuit of a shift register includes an output terminal, an input terminal, a reset terminal. A voltage is applied to a first wiring in response to the output signal from the preceding stage shift circuit to the input terminal and in accordance with the predetermined voltage to the first wiring, outputting an externally applied signal to the output terminal. A voltage level of the first wiring is reduced in response to the output signal to the reset terminal by the preceding stage shift circuit. The voltage is applied to the second wiring in response to a change in the level of the voltage applied to the first wiring. The voltage is applied to a second wiring in response to the output signal to the reset terminal by the preceding stage shift circuit. A voltage level of the output signal is reduced in response to the predetermined voltage to the second wiring.

Abstract: An output circuit which outputs an output signal voltage corresponding to an input signal voltage in a semiconductor circuit of this invention includes first and second voltage follower circuits. The input signal voltage is applied to the first voltage follower circuit from which the output signal voltage is output. The output signal voltage is negatively fed back to the first voltage follower circuit through the second voltage follower circuit so that the shift between the input and output signal voltages is suppressed. The first and second voltage follower circuits include a plurality of thin-film transistors.

Abstract: A shift register includes stages, outputting an output signal from each stage. The stage includes a first transistor which outputs an output signal inputted into one terminal from the previous stage via the other terminal, when an output signal is inputted into its control terminal. A second transistor has a control terminal connected to the other terminal of the first transistor, accumulates charges in a capacity of a wiring between the control terminal and the other terminal of the first transistor by a clock signal inputted into one terminal and outputs the clock signal from one terminal. A circuit displaces a potential of the wiring to a predetermined level when the output signal is inputted from the subsequent stage, and holds the potential of the wiring at a predetermined level until the output signal is inputted.

Abstract: A current generation supply circuit which supplies drive currents corresponding to digital signals for a plurality of loads comprising a current generation circuit which supplies output currents to the loads as the drive currents comprising a reference voltage generation circuit in which reference current having a constant current value is supplied and generates reference voltages based on the reference current; a drive current generation circuit which generates the output currents having current value ratios corresponding to the digital signals relative to the reference current based on the reference voltages; and a characteristic control circuit which sets the ratio of the output currents relative to the reference current.

Abstract: A current generation supply circuit which supplies drive currents corresponding to digital signals for a plurality of loads comprising a signal holding circuit which takes in and holds the digital signals, a current generation circuit which generates the drive currents having a ratio of current values corresponding to the values of the digital signals held in the signal holding circuit relative to the reference current supplied from a constant current source and supplied to the loads, and an operational state setting circuit which overlaps in terms of time and sets the operating state in the signal holding circuit and the current generation circuit in order to execute at least a take-in and hold operation of the digital signals in the signal holding circuit and a generation supply operation of the drive currents in the current generation circuit; as well as raises the operating speed of the current generation supply circuit.

Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.