Patents by Inventor Katsuhiko Nakai

Katsuhiko Nakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110084366
    Abstract: The epitaxial layer defects generated from voids of a silicon substrate wafer containing added hydrogen are suppressed by a method for producing an epitaxial wafer by: growing a silicon crystal by the Czochralski method comprising adding hydrogen and nitrogen to a silicon melt and growing from the silicon melt a silicon crystal having a nitrogen concentration of from 3×1013 cm?3 to 3×1014 cm?3, preparing a silicon substrate by machining the silicon crystal, and forming an epitaxial layer at the surface of the silicon substrate.
    Type: Application
    Filed: October 1, 2010
    Publication date: April 14, 2011
    Applicant: SILTRONIC AG
    Inventors: Katsuhiko Nakai, Timo Mueller, Atsushi Ikari, Wilfried von Ammon, Martin Weber
  • Patent number: 7875115
    Abstract: This disclosure is aimed at providing a method for producing an epitaxial wafer allowing uniform occurrence of oxygen precipitate in a substrate plane in the radial direction in a base plate and excelling in the crystal quality of an epi-layer. A method for the production of an epitaxial wafer, characterized by using as a substrate a base plate of nitrogen- and carbon-added silicon single crystal having a nitrogen concentration of 5×1014 to 5×1015 atoms/cm3 and a carbon concentration of 1×1016 to 1×1018 atoms/cm3, having a crystal growth condition during the production of silicon single crystal in a range in which the whole surface of substrate becomes an OSF region, and being pulled at a cooling speed of not less than 4° C./minute between 1100 and 1000° C. during the growth of crystal, and depositing the silicon single crystal layer on the surface of the substrate by the epitaxial method.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: January 25, 2011
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Koji Fukuhara
  • Publication number: 20100164071
    Abstract: Silicon wafers having excellent voltage resistance characteristics of an oxide film and high C-mode characteristics are derived from single crystal silicon ingots doped with nitrogen and hydrogen, characterized in that a plurality of voids constituting a bubble-like void aggregates are present ?50% relative to total voids; a V1 region having a void density of over 2×104/cm3 and below 1×105/cm3 is ?20% of the total area of wafer; a V2 region having a void density of 5×102 to 2×104/cm3 occupies ?80% of the total area of the wafer; and bulk microdefect density is ?5×108/cm3.
    Type: Application
    Filed: December 16, 2009
    Publication date: July 1, 2010
    Applicant: Siltronic AG
    Inventors: Katsuhiko Nakai, Atsushi Ikari, Masamichi Ohkubo
  • Publication number: 20100163807
    Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.
    Type: Application
    Filed: December 15, 2009
    Publication date: July 1, 2010
    Applicant: SILTRONIC AG
    Inventors: Masayuki Fukuda, Katsuhiko Nakai
  • Publication number: 20100155903
    Abstract: An annealed wafer having enhanced gettering effects for Cu is produced by heating a silicon substrate containing a nitrogen concentration of 5×1014 to 1×1016/cm3, a carbon concentration of 1×1015 to 5×1016/cm3, and an oxygen concentration of 6×1017 to 11×1017/cm3 at a temperature of 650 to 800° C. for a time ?4 hours, and subjecting the heated substrate to argon annealing at a temperature of 1100 to 1250° C., wherein internal stacking fault density after annealing is ?5×108/cm3.
    Type: Application
    Filed: December 9, 2009
    Publication date: June 24, 2010
    Applicant: Siltronic AG
    Inventors: Kazunori Ishisaka, Katsuhiko Nakai, Masayuki Fukuda
  • Publication number: 20100047563
    Abstract: Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 ?m from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ?1×1012/cm3, and the density of BSFs is ?1×108/cm3. The present silicon wafers preferably have an interstitial oxygen concentration of 4×1017 atoms/cm3 to 6×1017 atoms/cm3, and a density of BMDs with diagonal size of ?200 nm of not more than 1×107/cm3.
    Type: Application
    Filed: October 26, 2009
    Publication date: February 25, 2010
    Applicant: SILTRONIC AG
    Inventors: Katsuhiko Nakai, Masayuki Fukuda
  • Patent number: 7470323
    Abstract: The Czochralski method is used for producing p?-doped and epitaxially coated semiconductor wafers from silicon, wherein a silicon single crystal is pulled, and during the pulling is doped with boron, hydrogen and nitrogen, and the single crystal thus obtained is processed to form p?-doped semiconductor wafers which are epitaxially coated.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: December 30, 2008
    Assignee: Siltronic AG
    Inventors: Wilfried von Ammon, Katsuhiko Nakai, Martin Weber, Herbert Schmidt, Atsushi Ikari
  • Publication number: 20080131679
    Abstract: Silicon wafers and a process for their manufacture wherein both slip dislocation and occurrence of warpage are suppressed include heat treatment to provide wafers having plate-shaped BMDs, a density of BMDs whose diagonal lengths are in a range of 10 nm to 120 nm, of BMDs present in the bulk of the wafer at a distance of 50 ?m or more is 1×1011/cm3 or more, and the density of BMDs whose diagonal lengths are 750 nm or more in the wafer bulk is 1×107/cm3 or less, and the interstitial oxygen concentration is 5×1017 atoms/cm3 or less. The process involves low and high temperature heat treating at under defined temperature ramping rates.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 5, 2008
    Applicant: SILTRONIC AG
    Inventors: Katsuhiko Nakai, Sei Fukushima
  • Publication number: 20080113171
    Abstract: Silicon wafers having a density of BMDs with sizes between 20 to 40 nm at positions ?20 ?m below the wafer surface in the range of 5×1011/cm3, and a density of BMDs with sizes of ?300 nm?1×107/cm3, exhibit reduced slip dislocation and warpage. The wafers are sliced from a crystal grown under specific conditions and then subjected to both low temperature heat-treatment and high temperature anneal.
    Type: Application
    Filed: September 19, 2007
    Publication date: May 15, 2008
    Applicant: SILTRONIC AG
    Inventors: Katsuhiko Nakai, Wilfried von Ammon, Sei Fukushima, Herbert Schmidt, Martin Weber
  • Publication number: 20080096371
    Abstract: The Czochralski method is used for producing p?-doped and epitaxially coated semiconductor wafers from silicon, wherein a silicon single crystal is pulled, and during the pulling is doped with boron, hydrogen and nitrogen, and the single crystal thus obtained is processed to form p?-doped semiconductor wafers which are epitaxially coated.
    Type: Application
    Filed: October 11, 2007
    Publication date: April 24, 2008
    Applicant: SILTRONIC AG
    Inventors: Wilfried von Ammon, Katsuhiko Nakai, Martin Weber, Herbert Schmidt, Atsushi Ikari
  • Publication number: 20070178668
    Abstract: This disclosure is aimed at providing a method for producing an epitaxial wafer allowing uniform occurrence of oxygen precipitate in a substrate plane in the radial direction in a base plate and excelling in the crystal quality of an epi-layer. A method for the production of an epitaxial wafer, characterized by using as a substrate a base plate of nitrogen- and carbon-added silicon single crystal having a nitrogen concentration of 5×1014 to 5×1015 atoms/cm3 and a carbon concentration of 1×1016 to 1×1018 atoms/cm3, having a crystal growth condition during the production of silicon single crystal in a range in which the whole surface of substrate becomes an OSF region, and being pulled at a cooling speed of not less than 4° C./minute between 1100 and 1000° C. during the growth of crystal, and depositing the silicon single crystal layer on the surface of the substrate by the epitaxial method.
    Type: Application
    Filed: January 12, 2007
    Publication date: August 2, 2007
    Inventors: Katsuhiko Nakai, Koji Fukuhara
  • Publication number: 20070155134
    Abstract: An annealed wafer in which oxygen precipitation is uniform in the substrate plane and a manufacturing method thereof are provided. A nitrogen-doped silicon single crystal substrate pulled at the cooling rate of 4° C./minute or more during crystal growth between 1100 and 1000° C. wherein the nitrogen concentration is 1×1014 to 5×1015 atoms/cm3 and V/G satisfies predetermined conditions serves as a substrate, and the substrate is subjected to heat treatment in a non-oxidative atmosphere.
    Type: Application
    Filed: December 22, 2006
    Publication date: July 5, 2007
    Inventors: Katsuhiko Nakai, Koji Fukuhara
  • Patent number: 6548886
    Abstract: A silicon semiconductor substrate is obtained by deriving a silicon semiconductor substrate from a silicon single crystal grown by the Czochralski method from a molten silicon containing not less than 1×1016 atoms/cm3 and not more than 1.5×1019 atoms/cm3 of nitrogen and heat-treating the silicon semiconductor substrate at a temperature of not less than 1000° C. and not more than 1300° C. for not less than one hour and is characterized by the fact that the density of crystal defects measuring not less than 0.1 &mgr;m as reduced to diameter is not more than 104 pieces/cm3 at least in the region reaching a depth of 1 &mgr;m from the surface of the substrate and the nitrogen content at the center of thickness of the silicon semiconductor substrate is not less than 1×1013 atoms/cm3 and not more than 1×1016 atoms/cm3.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: April 15, 2003
    Assignee: Wacker NSCE Corporation
    Inventors: Atsushi Ikari, Masami Hasebe, Katsuhiko Nakai, Hikaru Sakamoto, Wataru Ohashi, Taizo Hoshino, Toshio Iwasaki