Abstract: A toner contained in a hopper is fed to an electrostatic conveyance member by a supply roller. With an actuator of the electrostatic conveyance member functioning, the toner is conveyed while being electrically charged at the same time, and is then supplied to a development roller. A thin layer of toner is formed on the development roller under the effect of an electric field. Since the toner is formed and charged without a mechanical layer thickness controlling member such as a doctor blade, mechanical stress acting on the toner is reduced.

Abstract: An image forming apparatus includes a latent image bearing member and a developing device for performing a two-level developing operation according to a threshold value of a potential on the latent image bearing member using a one-component developer including toner particles. The developing device has a conveyor to convey the developer to a developing area where the conveyor is spaced from the opposing latent image bearing member by a developing gap. The developing device also has a thin layer forming device to form the developer on the conveyor into a uniform thin layer. A developing bias voltage is applied to the conveyor when the two-level developing operation is performed and developing conditions are established such that an amount of the developer that is moved to and adheres to the latent image bearing member image area is saturated.

Abstract: An image forming apparatus of the present invention includes a bias power supply for applying a bias VB to a developer carrier on which a developer is deposited. A charge potential deposited on an image carrier, which faces the developer carrier for forming a latent image thereon, is 400 V or below in absolute value.

Abstract: A barrier layer (20, 62) for an integrated circuit structure is disclosed. The barrier layer (20, 62) is a refractory metal silicon compound, such as a refractor metal silicon nitride compound, formed in an amorphous state. The barrier layer (20, 62) has a relatively low composition ratio of silicon, and of nitrogen if present, to provide low resistivity in combination with the high diffusion barrier properties provided by the amorphous state of the film. A disclosed example of the barrier layer (20, 62) is a compound of tantalum, silicon, and nitrogen, formed by controlled co-sputtering of tantalum and silicon in a gas atmosphere including nitrogen and argon. The barrier layer (20) may be used to underlie copper metallization (22), or the barrier layer (62) may be part or all of a lower plate in a ferroelectric memory capacitor (70).

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: An image forming apparatus of the present invention includes a bias power supply for applying a bias VB to a developer carrier on which a developer is deposited. A charge potential deposited on an image carrier, which faces the developer carrier for forming a latent image thereon, is 400 V or below in absolute value. Assume that the potential of the image carrier is lowered to VL after exposure, that a development potential is |VB−VL|, that the maximum set value of the development potential for development is |VB−VL|max, and that the development potential varies in a range satisfying relations: |VB−VL|≦|VB−VL|max+|VB−VL|max×0.2 |VB−VL|≧|VB−VL|max−|VB−VL|max×0.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A plurality of types of engine units which have nonvolatile storage units and which have different performances, respectively, can be attached to an image formation apparatus main body in a replaceable manner. A control unit which controls the performance of an overall apparatus based on information stored in the storage units provided in the engine units, respectively, which are attached to the image formation apparatus main body, is provided in the image formation apparatus main body. Therefore, even if the image formation apparatus main body is common, the performance of the overall apparatus related to recording speed or resolution can be changed only by replacing the engine units different in performance. It is also possible to easily deal with various types of apparatuses.

Abstract: The development is performed under a condition that |Q2|−|Q1|/|Q1≦±0.45. Here, Q1 denotes an average amount of charge on toner held on a development roller and carried toward a development region immediately before development. Q2 denotes an average amount of charge on toner immediately before development held and carried toward the development region in the state immediately after development of an electrostatic latent image on a development drum. This is effective to allow the amount of charge q/m on toner held on the development roller to have a variation rate of 45% or below and an afterimage rate R within 2%.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: Monocolor image forming unit includes a developing device and an image carrier cleaning device arranged around an image carrier. A plurality of such the monocolor image forming unit is arrayed laterally along the rotary transport direction of an intermediate transfer member of the belt type to configure a tandem image forming device. In the tandem image forming device, a synthesized toner image is formed on the intermediate transfer member and transferred to a recording medium to form a multicolor image thereon. Among the plurality of monocolor image forming unit contained in the tandem image forming device, at least two monocolor image forming unit each include a toner recycling device for conveying toner collected at the image carrier cleaning device to the developing device.

Abstract: An image forming apparatus of the type which develops a latent image on an image carrier with toner stored in a developing unit and transferring the resulting toner image to a recording medium. The developing unit includes a developer carrier which contacts the image carrier at least at two spaced apart points with a gap being formed between the at least two points of contact. A moving mechanism will move opposite ends of the developer carrier independent distances relative to one another so as to eliminate the gap and establish full contact between the image carrier surface and developer carrier surface.

Abstract: An optical switch comprising an array of voltage-controlled interferometric switching elements. Different configurations and modes of operation are possible, but in each configuration the elements are arranged relative to the input and output fibers, such that a beam of light is incident or outgoing at an angle of 45 degrees to the surface of a corresponding element. This permits each element to be electronically controlled to either transmit or reflect light, such that the output beam exits the switch either parallel to or perpendicular to the input beam.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A developing device for an image forming apparatus of the type feeding a one-ingredient or two-ingredient type developer, forming a thin toner layer on a developing roller or toner support member and developing a latent image with the toner layer is disclosed. The toner support member has a surface that is chargeable to the same polarity as toner. The toner support member therefore serves to simply support the toner without electrostatically effecting the toner, so that the development of a latent image is free from the influence of the static electricity of the toner support member. This successfully enhances image quality. A photoconductive element has a coefficient of friction &mgr; confined in the range of 0.1<&mgr;<0.4, preventing the toner from depositing on and contaminating the background area of the element. In addition, the surface of the photoconductive element is protected and has its service life extended.

Abstract: The development is performed under a condition that |Q2|−|Q1|/|Q1≦±0.45. Here, Q1 denotes an average amount of charge on toner held on a development roller and carried toward a development region immediately before development. Q2 denotes an average amount of charge on toner immediately before development held and carried toward the development region in the state immediately after development of an electrostatic latent image on a development drum. This is effective to allow the amount of charge q/m on toner held on the development roller to have a variation rate of 45% or below and an afterimage rate R within 2%.

Abstract: An image forming apparatus of the present invention includes an image carrier made up of a conductive base and photoconductive layer and a toner carrier to which a bias for development is applied. The toner carrier conveys toner deposited thereon to a developing position where the toner carrier faces the image carrier, thereby developing a latent image formed on the image carrier. The apparatus effects low-voltage development that protects the image carrier from electrostatic fatigue, obviates background contamination, and realizes image density as high as 0.5 ×10−3 g/cm2 or above in terms of the amount of toner deposition. Further, the apparatus implements faithful development of the latent image by reducing the edge effect. An image forming process unit removable from the apparatus is also disclosed.