Patents by Inventor Katsuhiro Kondoh

Katsuhiro Kondoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5787191
    Abstract: A wiring pattern inspection apparatus for inspecting an abnormality of a wiring pattern formed on a printed circuit board, which is equipped with an optical image pickup device for optically illuminating a surface of the printed circuit board including the wiring pattern to photoelectrically convert optical information of the printed circuit board surface due to the optical illumination into a grey level image. This grey level image is converted into a bi-level image which separates the grey level image into the wiring pattern side and a background side of the wiring pattern. Thereafter, the bi-level image is once contracted by a first size and then expanded by a second size so as to eliminate a micro conductive portion left on the printed circuit board or a micro pinhole which can be disregarded in the abnormality inspection, thereby preventing the excessive detection.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: July 28, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Kawamura, Atsuharu Yamamoto, Yuji Maruyama, Hidehiko Kawakami, Katsuhiro Kondoh, Iwao Ichikawa
  • Patent number: 5459795
    Abstract: A wiring pattern inspection apparatus for inspecting an abnormality of a wiring pattern formed on a printed circuit board, which is equipped with an optical image pickup device for optically illuminating a surface of the printed circuit board including the wiring pattern to photoelectrically convert optical information of the printed circuit board surface due to the optical illumination into a grey level image. This grey level image is converted into a bi-level image which separates the grey level image into the wiring pattern side and a background side of the wiring pattern. Thereafter, the bi-level image is once contracted by a first size and then expanded by a second size so as to eliminate a micro conductive portion left on the printed circuit board or a micro pinhole which can be disregarded in the abnormality inspection, thereby preventing the excessive detection.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: October 17, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Kawamura, Atsuharu Yamamoto, Yuji Maruyama, Hidehiko Kawakami, Katsuhiro Kondoh, Iwao Ichikawa