Abstract: A communication processing system provided with one parent communication unit, at least one child communication unit, and at least one first detachable unit detachable from the at least one child unit, the system being operated in accordance with an operation program stored in a second detachable unit detachable from the parent unit, includes a transfer unit for transferring the operation program to the at least one child unit, a first storage unit for storing the operation program transferred from the parent unit by the transfer unit when the second detachable unit is mounted on the parent unit, the first storage unit being provided in the first detachable unit, and a second storage unit for storing a receiving program for receiving data sent from the parent unit, the second storage unit being provided in the first detachable unit. The first storage unit is provided in the first detachable unit. The second storage unit is provided in the first detachable unit.

Abstract: A data bus control circuit is formed on a single semiconductor integrated circuit that includes input/output terminals for external data exchange and a plurality of functional blocks including a CPU. A bi-directional bus buffer buffers data sent over a data bus between the CPU and the input/output terminals. The signal propagation direction of the bus buffer is determined according to a logic level of a read control signal supplied from the CPU.

Abstract: A microprocessor capable of executing a micro-instruction output from a micro-memory according to an address which corresponds to an instruction to be executed at a time when each time the microprocessor receives the address is provided. The microprocessor includes a unit (a T1 cycle signal generator, a T2 cycle signal generator, a TW cycle signal generator) for generating a control signal for a period of time corresponding to a period of time of a waiting signal at a time when the waiting signal is received from the outside, and a unit (a microcode read-only memory, a read-only memory address latch, a read-only memory output latch, an address control circuit, a multiplexer) connected to the control signal generating unit (the T1 cycle signal generator, the T2 cycle signal generator, the TW cycle signal generator) for holding an address supplied to the micro-memory for a period of time corresponding to a period of time of the control signal.