Patents by Inventor Katsuhiro Tomioka
Katsuhiro Tomioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972985Abstract: This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.Type: GrantFiled: December 25, 2019Date of Patent: April 30, 2024Assignee: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITYInventor: Katsuhiro Tomioka
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Publication number: 20220084891Abstract: This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.Type: ApplicationFiled: December 25, 2019Publication date: March 17, 2022Inventor: Katsuhiro TOMIOKA
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Patent number: 10403498Abstract: The present invention pertains to a group III-V compound semiconductor nanowire able to be used in a group III-V compound semiconductor MOSFET (FET) operational at a small subthreshold (100 mV/dec or less). A side face of the group III-V compound semiconductor nanowire is a (?110) plane constituted of a very small (111) plane. The group III-V compound semiconductor nanowire has, e.g., a first layer having a (111)A plane as a side face thereof, and a second layer having a (111)B plane as a side face thereof. The first layer and the second layer are stacked alternatingly in the axial direction.Type: GrantFiled: October 29, 2014Date of Patent: September 3, 2019Assignees: NATIONAL UNIVERSITY CORPORATION HAKKAIDO UNIVERSITY, JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Takashi Fukui, Katsuhiro Tomioka
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Patent number: 10381489Abstract: The tunnel field effect transistor according to the present invention has: a channel; a source electrode connected directly or indirectly to one end of the channel; a drain electrode connected directly or indirectly to the other end of the channel; and a gate electrode for causing an electric field to act on the channel, generating a tunnel phenomenon at the source electrode-side joint part of the channel, and simultaneously generating a two-dimensional electron gas in the channel.Type: GrantFiled: September 27, 2016Date of Patent: August 13, 2019Assignees: National University Corporation Hokkaido University, Japan Science and Technology AgencyInventors: Takashi Fukui, Katsuhiro Tomioka
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Publication number: 20180294362Abstract: The tunnel field effect transistor according to the present invention has: a channel; a source electrode connected directly or indirectly to one end of the channel; a drain electrode connected directly or indirectly to the other end of the channel; and a gate electrode for causing an electric field to act on the channel, generating a tunnel phenomenon at the source electrode-side joint part of the channel, and simultaneously generating a two-dimensional electron gas in the channel.Type: ApplicationFiled: September 27, 2016Publication date: October 11, 2018Inventors: Takashi FUKUI, Katsuhiro TOMIOKA
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Patent number: 9634114Abstract: A tunnel field-effect transistor (TFET) is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting p-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. Alternatively, the tunnel field-effect transistor is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting n-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. The nano wire is configured from a first region and a second region. For instance, the first region is intermittently doped with a p-type dopant, and the second region is doped with an n-type dopant.Type: GrantFiled: August 12, 2014Date of Patent: April 25, 2017Assignees: National University Corporation Hakkaido University, Japan Science and Technology AgencyInventors: Takashi Fukui, Katsuhiro Tomioka
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Publication number: 20160284536Abstract: The present invention pertains to a group III-V compound semiconductor nanowire able to be used in a group III-V compound semiconductor MOSFET (FET) operational at a small subthreshold (100 mV/dec or less). A side face of the group III-V compound semiconductor nanowire is a (?110) plane constituted of a very small (111) plane. The group III-V compound semiconductor nanowire has, e.g., a first layer having a (111)A plane as a side face thereof, and a second layer having a (111)B plane as a side face thereof. The first layer and the second layer are stacked alternatingly in the axial direction.Type: ApplicationFiled: October 29, 2014Publication date: September 29, 2016Applicants: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY, JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Takashi FUKUI, Katsuhiro TOMIOKA
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Publication number: 20160204224Abstract: A tunnel field-effect transistor (TFET) is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting p-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. Alternatively, the tunnel field-effect transistor is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting n-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. The nano wire is configured from a first region and a second region. For instance, the first region is intermittently doped with a p-type dopant, and the second region is doped with an n-type dopant.Type: ApplicationFiled: August 12, 2014Publication date: July 14, 2016Inventors: Takashi FUKUI, Katsuhiro TOMIOKA
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Patent number: 8895958Abstract: Disclosed is a light emitting element, which emits light with small power consumption and high luminance. The light emitting element has: a IV semiconductor substrate; two or more core multi-shell nanowires disposed on the IV semiconductor substrate; a first electrode connected to the IV semiconductor substrate; and a second electrode, which covers the side surfaces of the core multi-shell nanowires, and which is connected to the side surfaces of the core multi-shell nanowires. Each of the core multi-shell nanowires has: a center nanowire composed of a first conductivity type III-V compound semiconductor; a first barrier layer composed of the first conductivity type III-V compound semiconductor; a quantum well layer composed of a III-V compound semiconductor; a second barrier layer composed of a second conductivity type III-V compound semiconductor; and a capping layer composed of a second conductivity type III-V compound semiconductor.Type: GrantFiled: June 4, 2010Date of Patent: November 25, 2014Assignees: National University Corporation Hokkaido University, Sharp Kabushiki KaishaInventors: Takashi Fukui, Katsuhiro Tomioka
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Patent number: 8816324Abstract: Disclosed is a semiconductor device (10) which comprises a glass substrate (12), a lower electrode layer (14), an n-type doped polycrystalline silicon semiconductor layer (16), a low-temperature insulating film (20) in which openings (22, 23) that serve as nuclei for growth of a nanowire (32) are formed, the nanowire (32) that is grown over the low-temperature insulating film (20) and has a core-shell structure, an insulating layer (50) that surrounds the nanowire (32), and an upper electrode layer (52). The nanowire (32) comprises an n-type GaAs core layer and a p-type GaAs shell layer. Alternatively, the nanowire can be formed as a nanowire having a quantum well structure, and InAs that can allow reduction of the process temperature can be used for the nanowire.Type: GrantFiled: February 23, 2011Date of Patent: August 26, 2014Assignees: National University Corporation Hokkaido University, Sharp Kabushiki KaishaInventors: Takashi Fukui, Katsuhiro Tomioka, Junichi Motohisa, Shinjiroh Hara
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Patent number: 8698254Abstract: A tunnel field effect transistor is capable of operating at a low subthreshold and is able to be manufactured easily. The tunnel field effect transistor includes a group IV semiconductor substrate having a (111) surface and doped so as to have a first conductivity type, a group III-V compound semiconductor nanowire arranged on the (111) surface and containing a first region connected to the (111) surface and a second region doped so as to have a second conductivity type, a source electrode connected to the group IV semiconductor substrate; a drain electrode connected to the second region, and a gate electrode for applying an electric field to an interface between the (111) surface and the group III-V compound semiconductor nanowire, or an interface between the first region and the second region.Type: GrantFiled: September 29, 2010Date of Patent: April 15, 2014Assignee: National University Corporation Hokkaido UniversityInventors: Katsuhiro Tomioka, Takashi Fukui, Tomotaka Tanaka
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Publication number: 20120313078Abstract: Disclosed is a semiconductor device (10) which comprises a glass substrate (12), a lower electrode layer (14), an n-type doped polycrystalline silicon semiconductor layer (16), a low-temperature insulating film (20) in which openings (22, 23) that serve as nuclei for growth of a nanowire (32) are formed, the nanowire (32) that is grown over the low-temperature insulating film (20) and has a core-shell structure, an insulating layer (50) that surrounds the nanowire (32), and an upper electrode layer (52). The nanowire (32) comprises an n-type GaAs core layer and a p-type GaAs shell layer. Alternatively, the nanowire can be formed as a nanowire having a quantum well structure, and InAs that can allow reduction of the process temperature can be used for the nanowire.Type: ApplicationFiled: February 23, 2011Publication date: December 13, 2012Inventors: Takashi Fukui, Katsuhiro Tomioka, Junichi Motohisa, Shinjiroh Hara
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Publication number: 20120235117Abstract: Disclosed is a light emitting element, which emits light with small power consumption and high luminance. The light emitting element has: a IV semiconductor substrate; two or more core multi-shell nanowires disposed on the IV semiconductor substrate; a first electrode connected to the IV semiconductor substrate; and a second electrode, which covers the side surfaces of the core multi-shell nanowires, and which is connected to the side surfaces of the core multi-shell nanowires. Each of the core multi-shell nanowires has: a center nanowire composed of a first conductivity type III-V compound semiconductor; a first barrier layer composed of the first conductivity type III-V compound semiconductor; a quantum well layer composed of a III-V compound semiconductor; a second barrier layer composed of a second conductivity type III-V compound semiconductor; and a capping layer composed of a second conductivity type III-V compound semiconductor.Type: ApplicationFiled: June 4, 2010Publication date: September 20, 2012Applicant: National University Corporation Hokkaido UniversityInventors: Takashi Fukui, Katsuhiro Tomioka
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Publication number: 20120187376Abstract: A tunnel field effect transistor is capable of operating at a low subthreshold and is able to be manufactured easily. The tunnel field effect transistor includes a group IV semiconductor substrate having a (111) surface and doped so as to have a first conductivity type, a group III-V compound semiconductor nanowire arranged on the (111) surface and containing a first region connected to the (111) surface and a second region doped so as to have a second conductivity type, a source electrode connected to the group IV semiconductor substrate; a drain electrode connected to the second region, and a gate electrode for applying an electric field to an interface between the (111) surface and the group III-V compound semiconductor nanowire, or an interface between the first region and the second region.Type: ApplicationFiled: September 29, 2010Publication date: July 26, 2012Inventors: Katsuhiro Tomioka, Takashi Fukui, Tomotaka Tanaka