Patents by Inventor Katsuhisa Kugimiya
Katsuhisa Kugimiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240107786Abstract: A solid-state imaging element (1) according to the present disclosure includes a pixel array unit (10) in which a plurality of light receiving pixels (11) is two-dimensionally arranged. Each of the light receiving pixels (11) includes an organic photoelectric conversion unit (61) and another photoelectric conversion unit. The organic photoelectric conversion unit (61) includes a photoelectric conversion layer (63) made of an organic semiconductor material, a first electrode (62) located on a light incident side of the photoelectric conversion layer (63), and a second electrode (65) located on a side opposite to the light incident side of the photoelectric conversion layer (63). The other photoelectric conversion unit is located on a side opposite to the light incident side of the organic photoelectric conversion unit (61), and performs photoelectric conversion in a wavelength region different from a wavelength region of the organic photoelectric conversion unit (61).Type: ApplicationFiled: December 7, 2021Publication date: March 28, 2024Inventor: KATSUHISA KUGIMIYA
-
Publication number: 20230131416Abstract: Strength of an imaging element in which separation portions are disposed at boundaries of pixels is improved. The imaging element includes a plurality of pixels, separation portions, light blocking films, and separation portion protection films. The plurality of pixels include photoelectric conversion units that are formed on a semiconductor substrate and perform photoelectric conversion of incident light. The separation portions are disposed at boundaries of the plurality of pixels and separate the photoelectric conversion units from each other. The light blocking films are disposed near the boundaries of the plurality of pixels and block the incident light. The separation portion protection films are disposed adjacent to the separation portions and protect the separation portions.Type: ApplicationFiled: February 15, 2021Publication date: April 27, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Katsuhisa KUGIMIYA
-
Publication number: 20200057149Abstract: The present technology relates to an optical sensor that can suppress a decrease in distance measurement accuracy without increasing power consumption, and an electronic device. The optical sensor includes: a TOF pixel that receives reflected light which is returned when irradiation light emitted from a light emitting unit is reflected on a subject; and a plurality of polarization pixels that respectively receives light beams of a plurality of polarization planes, the light beams being a part of light from the subject. The present technology can be applied to, for example, the cases where distance measurement is performed.Type: ApplicationFiled: April 27, 2018Publication date: February 20, 2020Applicant: SONY CORPORATIONInventors: Katsuhisa KUGIMIYA, Hiroshi TAKAHASHI, Kenji AZAMI
-
Patent number: 10375282Abstract: The present technique relates to a camera module and an electronic apparatus that allow a camera module to be used for various purposes. The camera module includes a first pixel array in which pixels that receive light having an R, G, or B wavelength are two-dimensionally arranged in a matrix form and a second pixel array in which pixels that receive light having a wavelength region of visible light are two-dimensionally arranged in a matrix form and a first optical unit that converges incident light onto the first pixel array and a second optical unit that converges the incident light onto the second pixel array. The present technique can be for example applied to a camera module and the like.Type: GrantFiled: November 10, 2016Date of Patent: August 6, 2019Assignee: Sony Semiconductor Solutions CorporationInventors: Minoru Ishida, Katsuhisa Kugimiya, Hironori Hoshi
-
Publication number: 20180270404Abstract: The present technique relates to a camera module and an electronic apparatus that allow a camera module to be used for various purposes. The camera module includes a first pixel array in which pixels that receive light having an R, G, or B wavelength are two-dimensionally arranged in a matrix form and a second pixel array in which pixels that receive light having a wavelength region of visible light are two-dimensionally arranged in a matrix form and a first optical unit that converges incident light onto the first pixel array and a second optical unit that converges the incident light onto the second pixel array. The present technique can be for example applied to a camera module and the like.Type: ApplicationFiled: November 10, 2016Publication date: September 20, 2018Inventors: Minoru ISHIDA, Katsuhisa KUGIMIYA, Hironori HOSHI
-
Patent number: 9917091Abstract: A method of manufacturing a semiconductor device, includes: forming an insulating film on a first surface of a semiconductor substrate; and forming a hydrogen supply film on a second surface facing the first surface of the semiconductor substrate, the hydrogen supply film containing one or more of silicon oxide, TEOS, BPSG, BSG, PSG, FSG, carbon-containing silicon oxide, silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon carbide.Type: GrantFiled: May 28, 2015Date of Patent: March 13, 2018Assignee: SONY CORPORATIONInventors: Katsuhisa Kugimiya, Kenichi Murata, Hitoshi Okano, Shigetaka Mori, Hiroyuki Kawashima, Takuma Matsuno
-
Publication number: 20170207223Abstract: A method of manufacturing a semiconductor device, includes: forming an insulating film on a first surface of a semiconductor substrate; and forming a hydrogen supply film on a second surface facing the first surface of the semiconductor substrate, the hydrogen supply film containing one or more of silicon oxide, TEOS, BPSG, BSG, PSG, FSG, carbon-containing silicon oxide, silicon nitride, carbon-containing silicon nitride, and oxygen-containing silicon carbide.Type: ApplicationFiled: May 28, 2015Publication date: July 20, 2017Inventors: KATSUHISA KUGIMIYA, KENICHI MURATA, HITOSHI OKANO, SHIGETAKA MORI, HIROYUKI KAWASHIMA, TAKUMA MATSUNO
-
Patent number: 7977140Abstract: A method for producing a solid-state imaging device includes steps of: forming transfer electrodes on a substrate having a plurality of light-sensing portions through a gate insulating layer so that the light-sensing portions are exposed; forming a planarized insulating layer on the substrate to cover the transfer electrodes formed on the substrate; forming openings in the planarized insulating layer so that each of the transfer electrodes is partly exposed out of the planarized insulating layer at a predetermined position; forming a wiring material layer so that the openings are filled with the wiring material layer; forming a resist layer on the wiring material layer; exposing and developing the resist layer so that only the resist layer in a predetermined area covering the openings is left; and patterning the wiring material layer using the exposed and developed resist layer to form connection wirings connected to the transfer electrodes by the openings.Type: GrantFiled: March 23, 2009Date of Patent: July 12, 2011Assignee: Sony CorporationInventors: Takeshi Takeda, Yukihiro Ando, Masaki Okamoto, Masayuki Okada, Kaori Takimoto, Katsuhisa Kugimiya, Tadayuki Kimura
-
Publication number: 20090263929Abstract: A method for producing a solid-state imaging device includes steps of: forming transfer electrodes on a substrate having a plurality of light-sensing portions through a gate insulating layer so that the light-sensing portions are exposed; forming a planarized insulating layer on the substrate to cover the transfer electrodes formed on the substrate; forming openings in the planarized insulating layer so that each of the transfer electrodes is partly exposed out of the planarized insulating layer at a predetermined position; forming a wiring material layer so that the openings are filled with the wiring material layer; forming a resist layer on the wiring material layer; exposing and developing the resist layer so that only the resist layer in a predetermined area covering the openings is left; and patterning the wiring material layer using the exposed and developed resist layer to form connection wirings connected to the transfer electrodes by the openings.Type: ApplicationFiled: March 23, 2009Publication date: October 22, 2009Applicant: Sony CorporationInventors: Takeshi Takeda, Yukihiro Ando, Masaki Okamoto, Masayuki Okada, Kaori Takimoto, Katsuhisa Kugimiya, Tadayuki Kimura
-
Publication number: 20070298615Abstract: A pattern forming method is provided. The pattern forming method includes a first step of forming a resist pattern including a lactone group-containing skeleton above an etched layer provided on a substrate; a second step of performing plasma processing using a hydrogen-containing gas to lower a glass transition temperature or a softening point of the resist pattern; and a third step of transferring the resist pattern after the plasma processing to the etched layer by etching, and forming the pattern of the etched layer.Type: ApplicationFiled: January 30, 2007Publication date: December 27, 2007Inventors: Nobuyuki Matsuzawa, Atsuhiro Ando, Eriko Matsui, Yuko Yamaguchi, Katsuhisa Kugimiya, Tetsuya Tatsumi, Salam Kazi, Takeshi Iwai, Makiko Irie
-
Patent number: 6767821Abstract: A method of fabricating an interconnect line comprises forming a wall, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at the bottom to form the interconnect line having a pre-determined gap between the substrate and a bottom of the line.Type: GrantFiled: April 7, 2003Date of Patent: July 27, 2004Inventors: Chan-syun David Yang, Ajay Kumar, Wei-Te Wu, Changhun Lee, Yeajer Arthur Chen, Katsuhisa Kugimiya
-
Patent number: 6277763Abstract: A method and apparatus for etching of a substrate comprising both a polysilicon layer and an overlying tungsten layer. The method comprises etching the tungsten layer in a chamber using a plasma formed from a gas mixture comprising a fluorinated gas (such as CF4, NF3, SF6, and the like) and oxygen.Type: GrantFiled: December 16, 1999Date of Patent: August 21, 2001Assignee: Applied Materials, Inc.Inventors: Katsuhisa Kugimiya, Takanori Nishizawa, Daisuke Tajima