Abstract: A seal structure is a seal structure configured to seal, by using a seal material, between a first opposing surface and a second opposing surface which are opposed to each other. A second part includes an insertion hole which is open on the second opposing surface and into which a fastener is inserted; a chamfered surface including a first end connected to an edge of the second opposing surface, the chamfered surface being inclined relative to the second opposing surface; an end surface including an edge connected to a second end of the chamfered surface, the end surface being inclined relative to the chamfered surface. A space sandwiched between the chamfered surface and the first opposing surface forms a chamfered portion accommodating the seal material protruding from between the first opposing surface and the second opposing surface.

Abstract: A seal structure is a seal structure configured to seal, by using a seal material, between a first opposing surface and a second opposing surface which are opposed to each other. A second part includes an insertion hole which is open on the second opposing surface and into which a fastener is inserted; a chamfered surface including a first end connected to an edge of the second opposing surface, the chamfered surface being inclined relative to the second opposing surface; an end surface including an edge connected to a second end of the chamfered surface, the end surface being inclined relative to the chamfered surface. A space sandwiched between the chamfered surface and the first opposing surface forms a chamfered portion accommodating the seal material protruding from between the first opposing surface and the second opposing surface.

Abstract: A semiconductor device is composed of a heat sink, an IC chip mounted and fixed on a specific face of the heat sink, a lead frame electrically connected to the IC chip and a sealing mold resin package. One or more of the faces of the heat sink has a specific surface area.

Abstract: An operation switching circuit switches over two comparators, which receives communication data, in accordance with a normal mode and a standby mode of a microcomputer. A delay circuit delays a mode switching signal. The mode switching signal and the delayed signal are combined by an OR gate and an AND gate to two comparator control signals, which have different high level periods. The comparators are driven by the comparator control signals, while a multiplexer is driven by the delayed signal. When one comparator is switched from the inoperative state to the operative state, the other comparator is continued to be held operative for the delay period before being switched to the inoperative state.

Abstract: An operation switching circuit switches over two comparators, which receives communication data, in accordance with a normal mode and a standby mode of a microcomputer. A delay circuit delays a mode switching signal. The mode switching signal and the delayed signal are combined by an OR gate and an AND gate to two comparator control signals, which have different high level periods. The comparators are driven by the comparator control signals, while a multiplexer is driven by the delayed signal. When one comparator is switched from the inoperative state to the operative state, the other comparator is continued to be held operative for the delay period before being switched to the inoperative state.

Abstract: A semiconductor device is composed of a heat sink, an IC chip mounted and fixed on a specific face of the heat sink, a lead frame electrically connected to the IC chip and a sealing mold resin package. One or more of the faces of the heat sink has a specific surface area.

Abstract: A control system adaptable for use in controlling internal combustion engines has a microcomputer and a hardware circuit reconfigurable in internal logic circuitry in such a manner that the setting of configuration is completed before the microcomputer is rendered operative upon application of a power supply voltage. The microcomputer is assembled in a 4-V guarantee circuit block with its operating guarantee power supply voltage of 4 volts. A 3-V guarantee block includes a random logic circuit and an EEPROM for storage of circuit configuration set data. The 3-V guarantee block also includes a first power-on reset circuit for providing respective sections with a reset-release command signal when an applied power supply voltage potentially rises at 3 volts, and a second power-on reset circuit for forcing the random logic circuit in the reset state until completion of the reconfiguration of the hardware circuit.