Abstract: A selector selects an analog signal group to be used for PWM control out of a plurality of analog signals output by a PWM controlled load. An AD converter AD converts the analog signal group and generates a digital signal group that becomes control data for duty ratio setting in a duty ratio setting register to provide the generated digital signal group to a control unit for controlling a PWM circuit. A duty ratio comparison circuit compares duty ratios set by the plurality of duty ratio setting registers. An AD conversion channel selection circuit controls an analog signal group selecting operation by the selector based on a comparison result of the duty ratio comparison circuit.

Abstract: A selector selects an analog signal group to be used for PWM control out of a plurality of analog signals output by a PWM controlled load. An AD converter AD converts the analog signal group and generates a digital signal group that becomes control data for duty ratio setting in a duty ratio setting register to provide the generated digital signal group to a control unit for controlling a PWM circuit. A duty ratio comparison circuit compares duty ratios set by the plurality of duty ratio setting registers. An AD conversion channel selection circuit controls an analog signal group selecting operation by the selector based on a comparison result of the duty ratio comparison circuit.

Abstract: In the PWM circuit of the present invention, a PWM counter counts clock signals. A reference value setting register sets a comparative reference value for determining a duty ratio of a PWM signal. A comparator generates the PWM signals based on a comparative result of the comparative reference value and a count value of the PWM counter. A delay device delays the PWM signal. A switching device switchably outputs the output of the comparator and the output of the delay device in order of time sequence. Thereby, the pulse phase of the PWM signal can be adjusted.

Abstract: In the PWM circuit of the present invention, a PWM counter counts clock signals. A reference value setting register sets a comparative reference value for determining a duty ratio of a PWM signal. A comparator generates the PWM signals based on a comparative result of the comparative reference value and a count value of the PWM counter. A delay device delays the PWM signal. A switching device switchably outputs the output of the comparator and the output of the delay device in order of time sequence. Thereby, the pulse phase of the PWM signal can be adjusted.