Abstract: A multilayer interconnection structure of the present invention includes first interconnection, second interconnection belonging to an interconnection layer different from an interconnection layer to which the first layer belongs, and third interconnection for connecting the first and second interconnections, the third interconnection belonging to a different interconnection layer and including interconnection along a body diagonal for connecting two points in different planes belong to different interconnection layers. A method for producing the multilayer interconnection structure includes a step of forming the third interconnection, the step including a step of forming a through hole along the body diagonal, and a step of filling the through hole with a conductive material.

Abstract: A semiconductor device includes a substrate, a circuit pattern formed on the substrate, and a plurality of dummy patterns formed on the substrate in addition to the circuit pattern, wherein the plurality of dummy patterns include a plurality of marker dummy patterns in an array thereof, the marker dummy patterns being distinguishable from other dummy patterns and are distributed irregularly in the array of the dummy patterns.

Abstract: A multilayer interconnection structure of the present invention includes first interconnection, second interconnection belonging to an interconnection layer different from an interconnection layer to which the first layer belongs, and third interconnection for connecting the first and second interconnections, the third interconnection belonging to a different interconnection layer and including interconnection along a body diagonal for connecting two points in different planes belong to different interconnection layers. A method for producing the multilayer interconnection structure includes a step of forming the third interconnection, the step including a step of forming a through hole along the body diagonal, and a step of filling the through hole with a conductive material.

Abstract: A semiconductor device includes a substrate, a circuit pattern formed on the substrate, and a plurality of dummy patterns formed on the substrate in addition to the circuit pattern, wherein the plurality of dummy patterns include a plurality of marker dummy patterns in an array thereof, the marker dummy patterns being distinguishable from other dummy patterns and are distributed irregularly in the array of the dummy patterns.

Abstract: A pattern data inspection method includes the steps of (a) carrying out a logical/sizing process with respect to original pattern data, (b) carrying out a reverse-logical/reverse-sizing process with respect to pattern data subjected to the logical/sizing process, and (c) carrying out a logical process with respect to the original pattern data and pattern data subjected to the reverse-logical/reverse-sizing process, and inspecting the pattern data subjected to the logical/sizing process.

Abstract: A method and apparatus for inspecting patterns of reticle data includes carrying out a sizing process in which source data for designing a given device are combined with each other; carrying out a slit filling process in which any slit, that may occur in patterns obtained by the sizing process and is unconformable to a predetermined rule, is deleted by enlarging and reducing patterns; separately storing patterns obtained by the sizing process and patterns obtained by the slit filing process; carrying out a logical operation for patterns obtained by the sizing process and patterns obtained by the slit filling process; storing patterns obtained by logical operation as graphic patterns; detecting patterns each having dimensions equal to or smaller than the predetermined value on the basis of coordinates of the graphic patterns; and deeming the thus detected patterns to be false defect patterns and distinguishing false defect patterns from true defect patterns.

Abstract: A method and an apparatus for checking a mask pattern including a plurality of mask pattern regions formed based on different design pattern rules. The method includes the steps of: defining each of the mask pattern regions as a check object region; setting a defect detection reference corresponding to a respective design pattern rule of the mask pattern regions for each of the check object regions; and detecting presence or absence of defects in the mask pattern based on the respective defect detection reference for each of the check object regions. By these steps, it is possible to realize reduction in check time of the mask pattern and improvement in throughput of the checking apparatus, without necessitating discrimination processing of pseudo defects in the mask pattern.