Abstract: A display parameter synchronous holding circuit 20 comprises a register group 21 for receiving display parameters DP separated by variable length decoding circuit, a selector 24 for selecting and outputting either the display parameters DP or the output of the register group 21, register group 22 for receiving the output of the selector 24, a register group 23 for storing the output of the register group 22 in response to VSYNC, and a control circuit 25 for causing the selector 24 to select the output of the register group 21 and making latch signals SH2 and SH1 to register groups 22 and 21 active in the order when the picture coding type PCT indicates I-picture or P-picture, and for causing the selector 24 to select DP and making SH2 active when PCT indicates B-picture.

Abstract: A display parameter synchronous holding circuit 20 comprises a register group 21 for receiving display parameters DP separated by variable length decoding circuit, a selector 24 for selecting and outputting either the display parameters DP or the output of the register group 21, register group 22 for receiving the output of the selector 24, a register group 23 for storing the output of the register group 22 in response to VSYNC, and a control circuit 25 for causing the selector 24 to select the output of the register group 21 and making latch signals SH2 and SH1 to register groups 22 and 21 active in the order when the picture coding type PCT indicates I-picture or P-picture, and for causing the selector 24 to select DP and making SH2 active when PCT indicates B-picture.

Abstract: In storing decoded image data of a picture into a memory 23, PTS1 and a valid/invalid flag F1 corresponding to the picture are stored at the top boundary address ADR1 of a storage area within the memory 23, ADR1 is temporarily held in a register circuit 211. whether a read address ADR coincides with any one of addresses ADR1 to ADR3 within the register circuit 211 is detected while sequentially reading data from the memory 23 to display a picture. When coincidence is detected, the data read from the memory 23 are retrieved as PTS and F, and control corresponding to a time difference between STC and retrieved PTS is executed if F indicates validity. When coincidence is not detected, the data read from the memory 23 are used as display decoded image data DAT4.

Abstract: Control operations to access a memory changes respective priorities of the operations depending on the situation of the memory, and the operations are arbitrated and scheduled according to the respective, changed priorities, in order to avoid concentration on or rejection of a specific memory access operations and to eliminate an ineffective period. This realizes an efficient memory system without increasing the capacity of a buffer memory, the width of a memory bus, or an operating frequency.