Patents by Inventor Katsumasa Hashimoto

Katsumasa Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6287892
    Abstract: A plurality of substrate to which have been flip-chip mounted semiconductor chips are laminated by solder bumps provided for the purpose of lamination. A elastic resin is caused to fill the space between the chip upper surface and the substrate, thus providing a shock-absorbing material layer.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: September 11, 2001
    Assignee: NEC Corporation
    Inventors: Nobuaki Takahashi, Yoshitaka Kyougoku, Katsumasa Hashimoto, Shinichi Miyazaki
  • Patent number: 6025648
    Abstract: A plurality of substrates 1 to which have been flip-chip mounted semiconductor chips 2 are laminated by means of solder bumps 7 provided for the purpose of lamination. A elastic resin is caused to fill the space between the chip upper surface 9 and the substrate 1, thus providing a shock-absorbing material layer 8. By adopting this type of three-dimensional semiconductor modular structure, the shock-absorbing material layer 8 absorbs externally applied vibration and shock, thereby improving the immunity to vibration and shock.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: February 15, 2000
    Assignee: NEC Corporation
    Inventors: Nobuaki Takahashi, Yoshitaka Kyougoku, Katsumasa Hashimoto, Shinichi Miyazaki
  • Patent number: 5973392
    Abstract: A three-dimensional memory module includes a plurality of semiconductor device units, every adjacent two of which are stack-connected via through-holes by a bump connecting method. Each of the plurality of semiconductor device units includes a carrier having a circuit pattern and the through-holes connected to the circuit pattern. The semiconductor device unit also includes at least one semiconductor memory chip mounted on the carrier such that the semiconductor memory chip is connected to the circuit pattern, and at least one chip select semiconductor chip mounted on the carrier to be connected to the circuit pattern such that the chip select semiconductor chip can select the semiconductor memory chip.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventors: Naoji Senba, Yuzo Shimada, Ikusi Morizaki, Hideki Kusamitu, Makoto Ohtsuka, Katsumasa Hashimoto