Patents by Inventor Katsumi Ishikawa

Katsumi Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070221994
    Abstract: A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal of the switching device with reference to an emitter control terminal or a source control terminal of the switching device, and a unit for detecting a temperature of the switching device. The temperature of the power semiconductor switching device is detected, and a gate drive voltage or a gate drive resistance value is changed based on the detected temperature.
    Type: Application
    Filed: January 25, 2007
    Publication date: September 27, 2007
    Inventors: Katsumi Ishikawa, Sunao Funakoshi, Kozo Sakamoto, Hidekatsu Onose
  • Publication number: 20070216013
    Abstract: A power semiconductor module having an increased reliability against thermal fatigue includes a power semiconductor element, a lower-side electrode connected to the lower side of the element, a first insulating substrate connected to the upper side of the lower-side electrode and having metallic foils bonded on both surfaces thereof, an upper-side electrode connected to the upper side of the power semiconductor element, a second insulating substrate connected to the upper side of the upper-side electrode and having metallic foils bonded on both surfaces thereof, a first heat spreader connected to the lower side of the first insulating substrate, and a second heat spreader connected to the upper side of the second insulating substrate. The power semiconductor element and the first and second insulating substrates are sealed with a resin.
    Type: Application
    Filed: January 25, 2007
    Publication date: September 20, 2007
    Inventors: Sunao Funakoshi, Katsumi Ishikawa, Tasao Soga
  • Publication number: 20070200613
    Abstract: A gate driver circuit of a voltage drive type power semiconductor switching device capable of speeding up di/dt and dv/dt even during large-current driving to thereby reduce the switching loss is disclosed. This power semiconductor switching device gate driving circuit includes a drive circuit which applies a drive signal to the gate electrode of the power semiconductor switching device and a measurement unit for measuring a flow current of the power semiconductor switching device. Based on a detected value of the flow current of the power semiconductor switching device, the gate is made variable in mirror voltage thereof.
    Type: Application
    Filed: January 19, 2007
    Publication date: August 30, 2007
    Inventors: Katsumi Ishikawa, Yutaka Sato, Masahiro Nagasu, Seiji Ishida
  • Publication number: 20070200602
    Abstract: A gate driving circuit for a voltage-driven power semiconductor switching device has (a) the voltage-driven power semiconductor switching device, (b) a driving circuit for supplying a drive signal to the gate electrode of the switching device, and (c) an inductance between the emitter control terminal or source control terminal of the switching device and the emitter main terminal or source main terminal of a semiconductor module. A voltage produced across the inductance is detected. The gate-driving voltage or gate drive resistance is made variable based on the detected value.
    Type: Application
    Filed: January 19, 2007
    Publication date: August 30, 2007
    Inventors: Katsumi Ishikawa, Hideki Miyazaki, Masahiro Nagasu, Yasuhiko Kono
  • Publication number: 20070159171
    Abstract: Eddy current generated around a magnetic circuit in an MRI apparatus is one of the causes of deviation from an ideal magnetic field gradient waveform and causes image distortion, loss of strength, ghost generation, loss of signal, and spectral distortion. An object of the present invention is to suppress the generation of the eddy current. In an MRI apparatus, a ferromagnetic material formed from powder is used in a part of a magnetic circuit: the powder mainly comprising a mother phase containing iron or cobalt and showing ferromagnetism; and a high-resistance layer having a resistance not less than ten times as high as the mother phase and a Vickers hardness lower than that of the mother phase being formed in layers along parts of the surface of the powder on parts or the entire of the surface.
    Type: Application
    Filed: December 20, 2006
    Publication date: July 12, 2007
    Inventors: Matahiro Komuro, Yuichi Satsu, Takao Imagawa, Katsumi Ishikawa, Takeyuki Itabashi
  • Publication number: 20070151632
    Abstract: A lamellar high resistance layer having resistivity ten times or higher than that of a mother phase containing iron or cobalt is formed and an oxygen content is controlled to 10 to 10000 ppm so that the reliability and residual magnetic flux density are increased.
    Type: Application
    Filed: December 20, 2006
    Publication date: July 5, 2007
    Inventors: Matahiro Komuro, Yuichi Satsu, Takao Imagawa, Katsumi Ishikawa, Takeyuki Itabashi, Yuzo Kozono
  • Publication number: 20070103951
    Abstract: In a power conversion apparatus having a smoothing capacitor for smoothing rectified voltage, a power module containing a plurality of power semiconductor switching devices, and a drive circuit for controlling the turn-on and turn-off of the power semiconductor switching devices, wherein the power module is encased in the housing which does not encase the drive circuit; the housing encasing the power module therein is attached in contact with the housing encasing therein the transmission of an prime mover.
    Type: Application
    Filed: November 7, 2006
    Publication date: May 10, 2007
    Applicant: Hitachi, Ltd.
    Inventors: Katsumi Ishikawa, Hideki Miyazaki
  • Publication number: 20070030615
    Abstract: A drive circuit that controls a switching device ON/OFF and a soft cutoff command circuit that gradually decreases the gate terminal voltage of the switching device when short circuit of the switching device is detected. Additionally, an ON-pulse retention command circuit retains the output of the drive circuit ON when the gate terminal voltage is judged to have exceeded a specified value by a gate voltage judgment comparator that detects the gate terminal voltage of the switching device.
    Type: Application
    Filed: October 12, 2006
    Publication date: February 8, 2007
    Applicant: Hitachi, LTD.
    Inventors: Katsumi Ishikawa, Masataka Sasaki, Koichi Suda
  • Publication number: 20070001742
    Abstract: A level shifting circuit, satisfying a requirement of a high tolerated dV/dt level, and a highly reliable inverter circuit, wherein a set pulse signal and a reset pulse signal, both of which are level-shifted to a potential side taking as reference a reference potential of a gate control terminal of a switching terminal, are obtained differentially and integrated, and, in case these pulse signals equal or exceed stipulated integrated values, are transmitted as regular control signals controlling the on/off state.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Katsumi Ishikawa, Hideki Miyazaki, Koichi Suda, Katsunori Suzuki
  • Patent number: 7126802
    Abstract: A drive circuit 21 that controls a switching device 23 ON/OFF and a soft cutoff command circuit that gradually decreases the gate terminal voltage of the switching device 23 when short circuit of the switching device 23 is detected. Additionally, an ON-pulse retention command circuit 11 retains the output of the drive circuit 21 ON when the gate terminal voltage is judged to have exceeded a specified value by a gate voltage judgment comparator 16 that detects the gate terminal voltage of the switching device 23.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: October 24, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ishikawa, Masataka Sasaki, Koichi Suda
  • Publication number: 20060113668
    Abstract: A substrate package structure includes bumps disposed on a surface side of a first substrate and a surface side of a second substrate. The bump at the first substrate and the bump at the second substrate are press-fitted to each other while the one surface of the first substrate and the one surface of the second substrate are confronted to each other, thereby connecting the first and second substrates to each other. The bump at the first substrate is constructed so that the tip portion thereof is designed to have a flat surface, and the bump at the second substrate is constructed so that the tip portion is designed to have a projecting portion narrower than the tip portion of the bump at the first substrate.
    Type: Application
    Filed: November 21, 2005
    Publication date: June 1, 2006
    Applicant: DENSO CORPORATION
    Inventors: Katsumi Ishikawa, Hiroshi Takei, Nobuya Makino, Tetsuro Yano
  • Patent number: 7046155
    Abstract: A fault detection system detecting malfunctions or deteriorations, which may result in an inverter fault, is provided. The system has a temperature sensor installed on a semiconductor module to monitor a temperature rise rate. It is judged that an abnormal condition has occurred if the thermal resistance is increased by the deterioration of a soldering layer of the semiconductor module or by drive circuit malfunctions and, as a result, the relation between an operation mode and the temperature rise rate falls outside a predetermined range.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: May 16, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yutaka Sato, Masahiro Nagasu, Katsumi Ishikawa, Ryuichi Saito, Satoru Inarida
  • Publication number: 20060033552
    Abstract: To provide a highly reliable inverter apparatus which discriminates long-cycle noise generated by the isolated signal transmission element from short-cycle dv/dt noise and induction noise. A low pass filter, band pass filter, and a switching means are provided between the input section of the gate drive circuit of the voltage-drive type power semiconductor switching element and the isolated signal transmission means that transmits the output of the control circuit; and an abnormal signal discriminating circuit is also provided which turns on and off the switching means according to the output of the band pass filter thereby eliminating long-cycle noise derived from the isolated signal transmission element, short-cycle dv/dt noise, and induction noise; and also outputs alarm signals.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 16, 2006
    Applicant: Hitachi, Ltd.
    Inventors: Katsumi Ishikawa, Hideki Miyazaki, Koichi Suda
  • Publication number: 20050205995
    Abstract: A wire bonding method for bonding a plurality of conducting wires to connect first conductors and second conductors has the following steps. 1) Bonding a first conducting ball on a first first conductor. 2) Bonding a first conducting wire on the first conducting ball, the first conducting wire being connected to a first second conductor. 3) Bonding a second conducting ball on a second first conductor. 4) Bonding a second conducting wire on the second conducting ball, the second conducting wire being connected to a second second conductor. Here, the second first conductor or the second second conductor is the first conducting wire bonded on the first conducting ball.
    Type: Application
    Filed: February 24, 2005
    Publication date: September 22, 2005
    Inventors: Katsumi Ishikawa, Nobuya Makino, Hiroshi Takei
  • Publication number: 20050206141
    Abstract: An airbag is disclosed wherein a lower deployment portion, right deployment portion, and left deployment portion are folded on the occupant side of a central deployment portion in an optional order. The upper deployment portion is folded to be located on the most occupant side and upper side of the folded deployment portions.
    Type: Application
    Filed: February 25, 2005
    Publication date: September 22, 2005
    Inventors: Katsumi Ishikawa, Norimasa Goto
  • Publication number: 20050132726
    Abstract: The object of the invention is to provide an inverter system and vehicles using this inverter wherein accurate detection of the abnormal heat generation from the inverter is ensured, despite a large amount of noise signals, a substantial fluctuation in environmental temperature, or a change of cooling performances resulting from the environmental conditions. Based on the output value of an outside air temperature detecting means 150 and temperature calculation parameters inputted from outside the inverter system, the temperature calculation circuit 144B of an error detecting section 144 calculates the temperature Tcal where a temperature detecting means below semiconductor device 152 is installed.
    Type: Application
    Filed: August 18, 2004
    Publication date: June 23, 2005
    Applicant: HITACHI, LTD.
    Inventors: Masataka Sasaki, Hideki Miyazaki, Katsumi Ishikawa, Keiji Maekawa
  • Patent number: 6892564
    Abstract: An object of the present invention is to provide a fall impact apparatus, namely a fall impact apparatus, which is capable of fixing the attitudinal angle of a test subject during a drop test until the moment at which the test subject collides with a dropping subject surface. The fall impact apparatus includes a test subject fixing member for fixing a test subject which is to be tested for impact strength at a desired attitudinal angle, a hoisting and dropping member for raising and dropping the test subject fixing member to which the test subject is fixed along the falling direction of the test subject, and a dropping subject surface structured so as to collide only with the test subject at the terminal end of the falling direction without interfering with the hoisting and dropping member when the hoisting and dropping member is dropped together with the test subject fixing member.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: May 17, 2005
    Assignee: Uniden Corporation
    Inventor: Katsumi Ishikawa
  • Publication number: 20050016256
    Abstract: An object of the present invention is to provide a fall impact apparatus, namely a fall impact apparatus, which is capable of fixing the attitudinal angle of a test subject during a drop test until the moment at which the test subject collides with a dropping subject surface. The fall impact apparatus comprises a test subject fixing member for fixing a test subject which is to be tested for impact strength at a desired attitudinal angle, a hoisting and dropping member for raising and dropping the test subject fixing member to which the test subject is fixed along the falling direction of the test subject, and a dropping subject surface structured so as to collide only with the test subject at the terminal end of the falling direction without interfering with the hoisting and dropping member when the hoisting and dropping member is dropped together with the test subject fixing member.
    Type: Application
    Filed: December 23, 2003
    Publication date: January 27, 2005
    Inventor: Katsumi Ishikawa
  • Publication number: 20040252432
    Abstract: A collector voltage of a power management semiconductor device is detected by a first comparator, and when the detected collector voltage exceeds a first reference voltage, the first comparator outputs a first detection signal. Furthermore, a gate voltage of the power management semiconductor device is detected by a second comparator, and when the detected gate voltage exceeds a second reference voltage, the second comparator outputs a second detection signal. The second reference voltage is a minimum gate voltage for feeding a rated power to the power management semiconductor device or over, and less than a line power voltage of a drive circuit of the power management semiconductor device. When both the first detection signal and second detection signal are being outputted, the gate voltage is reduced by a gate voltage reduction means so as to protect the power management semiconductor device from overcurrent and overvoltage.
    Type: Application
    Filed: February 9, 2004
    Publication date: December 16, 2004
    Applicant: HITACHI, LTD.
    Inventors: Masataka Sasaki, Katsumi Ishikawa, Ryuichi Saito, Koichi Suda, Katsuaki Takahashi
  • Publication number: 20040252435
    Abstract: (Object) To offer such drive circuit for a switching device that can operate a soft cutoff function when short circuit is detected and also can be prevented from breakdown even if a narrow pulse is inputted.
    Type: Application
    Filed: February 24, 2004
    Publication date: December 16, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Katsumi Ishikawa, Masataka Sasaki, Koichi Suda