Abstract: The object of the invention is the provision of a semiconductor memory having processor and memory integrally mounted on one chip. To attain the object, crossbar wirings are laid on the memory cell area and crossbar switches are disposed in the sense amplifier area or word driver area. Accordingly, memory sharing is made possible without increasing the chip area and it is also made possible to take out a large number of data continuously. Hence, a memory-embedded system with a high bandwidth can be provided.

Abstract: A chip multiprocessor (CMP) includes a plurality of processors disposed on a peripheral region of a chip. Each processor has (a) a dual datapath for executing instructions, (b) a compiler controlled register file (RF), coupled to the dual datapath, for loading/storing operands of an instruction, and (c) a compiler controlled local memory (LM), a portion of the LM disposed to a left of the dual datapath and another portion of the LM disposed to a right of the dual datapath, for loading/storing operands of an instruction. The CMP also has a shared main memory disposed at a central region of the chip, a crossbar system for coupling the shared main memory to each of the processors, and a first-in-first-out (FIFO) system for transferring operands of an instruction among multiple processors.

Abstract: In a processor system configured to execute instructions, a method finds an entry in at least one table stored in memory. The method includes (a) storing a first table of multiple entries, each entry including a bit field; (b) storing (i) a first entry of the first table and (ii) a bit size of each entry; (c) storing a sequence of data bits; (d) selecting a portion of the sequence of data bits to produce a data field having a bit size same as the bit size of each entry in the first table; and (e) adding the first entry of the first table to the produced data field to find the entry in the first table.

Abstract: A processing system includes left and right data path processors configured to concurrently receive parallel instructions. Left and right accumulators which are, respectively, disposed in the left and right data path processors, are configured to execute an accumulate instruction and obtain an accumulation value. Left and right local memories (LMs) are coupled to the left and right accumulators and configured to store the accumulation value. The accumulation value is equally divided for storage in the left LM and the right LM.

Abstract: A data processing system includes left and right data path processors coupled to an instruction cache. The left and right data path processors, respectively, are configured to execute left and right instruction words received in a single clock cycle from the instruction cache. The left and right data path processors are also configured to operate in a scalar mode and a vector mode. The processors (a) execute the left and right instruction words as two separate instructions in the scalar mode, and (b) execute the left and right instruction words as one instruction in the vector mode.

Abstract: A processing system includes left and right data path processors configured to execute instructions issued from an instruction cache. A vector instruction includes a first word configured for execution by the left data path processor and a second word configured for execution by the right data path processor. The first and second words are issued in the same clock cycle from the instruction cache, and are interlocked to jointly specify a single vector instruction. The first and second words include code for vector operation and code for vector control. The first and second words are concurrently executed to complete the vector operation, free-of any other instructions issued from the instruction cache.

Abstract: A multiprocessor system for concurrently executing multiple tasks includes first and second processors, each configured to execute at least one task and a local memory physically disposed externally of, and concurrently accessible by the first and second processors. An operating system assigns: (a) a first task to the first processor and a second task to the second processor, the first and second tasks having respective execution resource requirements, (b) a first portion of the local memory to the first processor, and (c) a second portion of the local memory to the second processor. The operating system is configured to initially adjust the first and second portions of the local memory based on the respective execution resource requirements. Portions of the local memory assigned to be shared by the first and second processors may be cooperatively accessed by each of the processors without intervention by the operating system.

Abstract: The object of the invention is the provision of a semiconductor memory having processor and memory integrally mounted on one chip. To attain the object, crossbar wirings are laid on the memory cell area and crossbar switches are disposed in the sense amplifier area or word driver area. Accordingly, memory sharing is made possible without increasing the chip area and it is also made possible to take out a large number of data continuously. Hence, a memory-embedded system with a high bandwidth can be provided.

Abstract: The present invention relates to a magnetic disk control unit which can accomplish active interchange of firmwares. Thus, in this invention, a firmware constituting the magnetic disk control unit includes an internal table area for retaining various data necessary for control, a save area for temporarily saving, of the data in the internal table area, data necessary before and after interchange of the firmware while the firmware undergoes active interchange, a first interruption control section serving, as interruption handling functions, a normal function to refer to the internal table area in accordance with an interruption for advancing to processing to the interruption and a busy response function to perform a busy response to the host unit during the firmware active-interchange, and a second interruption control section serving, as an interruption handling function, only a busy response function to accomplish a busy response to the host unit during the firmware active-interchange.

Abstract: Disclosed is the powder feeder in which the duty ratio X.sub.T corresponding to the target feed amount Q.sub.T is calculated on the basis of the calibration curve obtained by the feeder calibration which is conducted before the start of powder feed, and the powder P starts to be fed according to the duty ratio X.sub.T, therefore, the actual feed amount can reach to the target feed amount Q.sub.T in a short time (within the time T.sub.1) from the start of powder feed, and the powder P can be fed while controlling the actual feed amount with high accuracy, and further the powder P can be precisely fed even in case of the short time feed for several seconds.

Abstract: Disclosed is the drive apparatus for the powder feeder, which has; the duty ratio control circuit 12 which applies the alternating voltage with the resonance frequency to the vibrator 10 during a time corresponding to the duty ratio; the current monitor 15 which detects the residual frequency of the electro motive force produced due to the residual oscillation of the vibrator 10 when the alternating voltage with the resonance frequency is not applied from the duty ratio control circuit 12 and feeds back the detected residual frequency to the PLL control circuit 11 through the zero-cross comparator 17.

Abstract: This invention provides a method for driving intermittently a vibrator having a resonance frequency with the resonance frequency in which the vibration of the resonance frequency is attenuated promptly after the ending of driving with the resonance frequency and the vibration of the resonance frequency increases promptly after the starting of driving with the resonance frequency. Further, this invention provides a method for driving powder feeders using ultrasonic motors which are easy to control powder feed rates and further provides powder feeders. A powder feed pipe is attached to an ultrasonic motor the end of which is elliptically vibrated with the resonance frequency, and powder P is fed from the hopper body when AC voltages of the resonance frequency and non-resonance frequency are applied alternately to the piezoelectric element 1 of the ultrasonic motor.

Abstract: Disclosed is the powder feeder in which the sampling timing G, H, . . . is set during the inactive period T.sub.i in synchronism with the cycle of the duty ratio clock when the output voltage V.sub.CELL is fed back to the microcomputer 13, thereby the feedback signal (the output voltage V.sub.CELL) on which noise is not superposed can be sampled and the feed amount of the powder P can be controlled with high accuracy.

Abstract: The present invention relates to an outline font expanding method and an outline font expanding device each of which can reproduce faithfully the line width of an original outline font. The coordinate system for vector data is defined on the boundaries between dots to create an outline font on the boundaries. The number of dots in the main scanning direction is calculated as a unit change when the outline font is moved by one dot in the secondary scanning direction. A value obtained by dividing the unit change by 2 is added to the coordinate in the main scanning direction of the outline font. while the scanning line is moved dot by dot in the main scanning direction, the intersection of the scanning line and the outline font is obtained at each move position. Thus, the filling range over the scanning line is defined in the main scanning direction.

Abstract: An apparatus for inputting and processing information through a keyboard comprises sensors for detecting that fingers of an operator have contacted with or approached keys on the keyboard, a signal processing device for inputting and processing the detection information from the sensors and information from switch circuits which are turned on or off upon operation of the keys on the keyboard, and a display unit for displaying the detection information from the sensors and the information from the switch circuits as information symbols, respectively, whereby a keyboard entry operation by the operator is made easy and comfortable, and, as a result, it becomes possible to prevent occurrence of a key entry error and to reduce the number of times of key operations.

Abstract: A data reproducing system is provided wherein data stored in an optical disk can be read and, in accordance with a coded error detection and correction code, can have an error pointer defined in synchronization with a modulated data of one symbol. This information can be transmitted, through a time division multiplexing circuit, at a faster clock speed than a demodulating clock with which the timing of a data demodulating will be controlled.

Abstract: A deinterleaving and error correction system which is advantageously utilized in a playback system of an optical recording disk apparatus. As each block of sector data, encoded for example with the Reed-Solomon error correction code with block interleaving, is read from the disk, the positions within the data block at which drop-out of the playback signal occurs are respectively stored in a memory in which the data symbols are also stored, with these drop-out positions being stored as error position data. Error correction processing is executed using the error position data in conjunction with the code words, enabling the maximum number of correctable errors for each sector to be substantially increased using a simple system configuration.

Abstract: An error detecting and correcting apparatus having a Galois field arithmetic unit for detecting and correcting errors in code words of a long minimum distance Reed-Solomon error correcting code used in recording/reproducing data to/from media such as an optical disk, by decoding the error correcting code.

Abstract: An information signal transmitting device which can transmit a large amount of information rapidly and readily with a simplified construction of a reduced size and can be produced at a reduced cost. The device comprises a movable unit and a fixed unit between which an information signal is transmitted using an electromagnetic wave or an ultrasonic wave as a transmitting medium. The movable unit includes a signal receiving means for converting an information signal transmitted from the fixed unit into a binary signal, a shift register for storing an output of the signal receiving means therein, and a signal transmitting means for transmitting one bit of an information signal outputted from the shift register.

Abstract: The present invention relates to a Galois field arithmetic logic unit of a code error check/correct apparatus to be employed when recording/reproducing data on an optical disk. The arithmetic logic unit uses a combination including a parallel multiplication circuitry of a primitive element .alpha. of a Galois field, an EX-OR addition circuitry for the multiplication resuts, a 0 element decision circuitry for the results of the addition, the registers to which the multiplication results are fed back so as to accomplish a parallel computation of a polynomial, thereby enabling a root and an error value of an error location equation to be obtained at a high speed. The arithmetic logic unit develops a remarkable reduction of the amount of computation particularly when the code system has a great code length and the degree of the error location polynomial associated with the long distance code is as high as d=17.