Abstract: The present invention relates to a resin composition for foam, which is used as a packing cushioning material, and an object thereof is to provide said composition which has biodegradability and is made from a principal raw material, lactic acid capable of contributing to the protection of global environment. The object can be attained by a resin composition having biodegradability and expandability, comprising a high-molecular weight polylactic acid having a melt viscosity of 0.01 to 50 in terms of a melt index value (MI), characterized in that said resin composition is prepared by compounding 0.1 to 5% by weight of at least one compound, which is selected from a polyisocyanate having an isocyanate group of not less than 2.0 equivalents/mol, an epoxy compound having an epoxy group of more than 2.0 equivalents/mol and an acid anhydride having an anhydrous carboxyl group of more than 2.

Abstract: A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse sets a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.

Abstract: A system for computer pipeline operation in which a plurality of instructions are executed in parallel by commencing, before the termination of execution of the preceding instruction, the execution of the present instruction, including a conflict detection unit, a data establishment indication unit, and a source data by-pass unit. The source data by-pass unit by-passes a source data to the processing stage which requires this source data immediately after conflict is detected between the result data of the preceding instruction and the source data of the present instruction and the establishment of the source data of the present instruction is detected.

Abstract: According to the present invention, a calculation for determining branching conditions is carried out during the fetching of the branch-to instruction. The branching instruction causes a branch to the specified branch-to address depending on whether an incremented index is larger or smaller than a comparison number. The determination is made by adding an increment to the index and comparing the result with the comparison number. These BXH and BXLE instructions can be processed at a high speed.

Abstract: A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse makes a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.

Abstract: The present invention includes a suboperation code control memory which stores data for generating a heading address of a microprogram for an instruction having a suboperation code. Access to an operation code control memory by the ordinary operation code and the access to suboperation code control memory are carried out simultaneously. The heading address of the microprogram is generated by editing the data read from the respective control memories. The storage capacity needed for the suboperation memory is reduced and still no problem occurs in assigning microinstruction addresses, and the heading address of a microprogram for the instruction having a relevant suboperation code is produced without any additional time.

Abstract: A system for controlling the transfer of commands between processors of a multiprocessor system, including a single control unit connected to all the processors by separate information transfer lines. The control unit selects the processor generating a command transfer request signal in a predetermined priority order and receives the processor address from the selected processor. The receiving processor and predetermined transfer information are determined in accordance with the selected processor, the processor address, and the processor status information determined by the processor address. The predetermined transfer information is transferred to the receiving processor via an information transfer path established between the selected processor and the receiving processor.

Abstract: According to the present invention, in a data processing unit which executes pipeline processings by developing an instruction into multiple flows through microprogram control, is a method provided where the microinstruction is divided into a part for controlling a first stage of pipeline and a part for controlling second and successive stages. The part for controlling the first stage is read simultaneously with the part for controlling the second and successive stages of the flow prior to the current flow. The present invention thus provides an advantage in that microprogram control can be employed for the first stage of the pipeline and resulting in a data processing unit which is capable of executing more flexible pipeline processings than the prior art can be formed.

Abstract: According to the present invention, an instruction address register unit I for reading instructions and an instruction address register unit II for indicating the address of the instruction being executed in the pipeline are provided independently. The address of a branching instruction is held in the instruction address register unit II until said instruction passes through the pipeline, the content of instruction address register unit I is updated when branching of the branching instruction is determined, and thereby delay in reading an instruction after 8 bytes at the branching address can be reduced.

Abstract: A computer system includes a processing unit; main storage; cache buffer storage provided between the processing unit and the main storage; and a store buffer device between the processing unit and main storage, receiving data identical to that stored in the cache buffer storage and control information in response to requests from the processing unit and transferring the data and control information to main storage. The transmission from the processing unit to the store buffer device and from the store buffer device to main storage are in a machine cycle. The store buffer device includes a controller, data register sets, each set including registers for receiving data to be stored in main storage, a byte mark register set of byte mark registers for information indicating storable data in the data registers, and an address register set of address registers for a starting store address in main storage for the data in the data registers.