Patents by Inventor Katsumi Shigenobu

Katsumi Shigenobu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7171592
    Abstract: A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: January 30, 2007
    Assignee: Fujitsu Limited
    Inventors: Kenji Togashi, Morihiko Hamada, Shigekazu Aoki, Katsumi Shigenobu, Yukio Saka, Yoshikazu Arisaka, Toyoji Sawada, Tadashi Asai
  • Publication number: 20030177415
    Abstract: A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.
    Type: Application
    Filed: February 10, 2003
    Publication date: September 18, 2003
    Applicant: Fujitsu Limited
    Inventors: Kenji Togashi, Morihiko Hamada, Shigekazu Aoki, Katsumi Shigenobu, Yukio Saka, Yoshikazu Arisaka, Toyoji Sawada, Tadashi Asai
  • Patent number: 5631866
    Abstract: A synchronous DRAM is disclosed. The DRAM comprises an input buffer, a memory cell array, an output buffer, a signal transfer circuit, first and second latch circuits, and a controller. The input buffer receives an operation control signal supplied externally. The memory cell array has a plurality of memory cells for storing data. The output buffer outputs a data signal read from the memory cells. The signal transfer circuit reads a data signal from one of the memory cells in accordance with the operation control signal from the input buffer, and sends this read data signal to the output buffer. The first and second latch circuits, provided between the input buffer and the output buffer, latch the associated input signals in response to a clock signal.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: May 20, 1997
    Assignee: Fujitsu Limited
    Inventors: Tomoharu Oka, Yukinori Kodama, Katsumi Shigenobu
  • Patent number: 5483497
    Abstract: A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.
    Type: Grant
    Filed: July 19, 1994
    Date of Patent: January 9, 1996
    Assignee: Fujitsu Limited
    Inventors: Hirohiko Mochizuki, Yoshihiro Takemae, Yukinori Kodama, Makoto Yanagisawa, Katsumi Shigenobu