Abstract: A central processing unit is cascade-connected with a plurality of I/O units, and a bus interconnecting them comprises a plurality of data lines for transmitting a control command signal, an address signal and a data signal on a time shared basis, a plurality of tag lines, each transmitting a tag signal indicating which one of the signals is provided on the data lines, and a clock line for transmitting a clock signal for these signals.

Abstract: A plurality of low-speed memories having stored therein a plurality of patterns and first and second high-speed memories of higher operating speed than the low-speed memories are provided. One of the first and second high-speed memories is read to obtain output patterns and, at the same time, the plurality of low-speed memories are simultaneously read and the read-out data are successively written in the other high-speed memory alternately with each other. Upon completion of pattern generation from the one high-speed memory, pattern generation from the other high-speed memory is achieved.