Patents by Inventor Katsumi Takeuchi

Katsumi Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097013
    Abstract: Provided is a semiconductor device capable of reducing switching loss at turn-off while suppressing conduction loss. An emitter p? layer 11, a collector p layer 23, a drift layer 10, an emitter electrode 18, a collector electrode 28, an emitter-side gate electrode 17, an emitter n layer 12, a collector p? layer 23a, a collector-side gate electrode 27, and a collector n layer 22 configure a semiconductor device 1, and a total length of a first facing region of the emitter-side gate electrode 17 in a gate width direction facing an emitter layer p? 11 via a gate insulating film 15 is longer than the total length in the gate width direction of a second facing region of a collector-side gate electrode 27 facing an impurity layer 23a via a collector-side gate insulating film 25.
    Type: Application
    Filed: November 16, 2021
    Publication date: March 21, 2024
    Inventors: Toshiro Hiramoto, Takuya Saraya, Kiyoshi Takeuchi, Kazuo Itou, Toshihiko Takakura, Munetoshi Fukui, Shinichi Suzuki, Katsumi Satoh, Tomoko Matsudai
  • Patent number: 8607443
    Abstract: A method of manufacturing a connector chip includes preparing a plate-like insulating substrate material with a plurality of through hole rows arranged therein; forming a plurality of first and second base layers on opposite surfaces of the insulating substrate material; forming insulating layers between each two adjoining first base layers and between each two adjoining second base layers; forming third base layers on the one side over edge portions of the first base layers, internal surfaces of the through holes, and edge portions of the second base layers; forming fourth base layers on the other side over edge portions of the first base layers, the internal surfaces of the through holes, and edge portions of the second base layers; cutting the insulating substrate material along a middle of each of the through hole rows; and forming one or more plated layers over the first to fourth base layers.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 17, 2013
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Shinji Okamoto, Katsumi Takeuchi, Yutaka Nomura
  • Patent number: 8193899
    Abstract: A chip-like electric component such as a chip resistor is provided, which is easy to manufacture and in which cracks or fractures of an insulating substrate are unlikely to occur. A pair of surface electrodes 21, 23 are formed so that thicknesses of the pair of surface electrodes increase from a resistor layer 13 toward end portions 30 of an insulating substrate 29 in a direction in which the pair of surface electrodes 21, 23 are arranged. A plating reservoir S is formed between one of the surface electrodes 21, 23 and an insulating protective layer 15. When forming at least one plated layer 33, a plated metal pools in the plating reservoir S. The at least one plated layer 33 may work to reduce to some extent a height difference between a soldering electrode portion 21, 23, 27, 33 and the insulating protective layer 15.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: June 5, 2012
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Katsumi Takeuchi, Yutaka Nomura, Hiroyuki Kurokawa
  • Publication number: 20110080251
    Abstract: A chip-like electric component such as a chip resistor is provided, which is easy to manufacture and in which cracks or fractures of an insulating substrate are unlikely to occur. A pair of surface electrodes 21, 23 are formed so that thicknesses of the pair of surface electrodes increase from a resistor layer 13 toward end portions 30 of an insulating substrate 29 in a direction in which the pair of surface electrodes 21, 23 are arranged. A plating reservoir S is formed between one of the surface electrodes 21, 23 and an insulating protective layer 15. When forming at least one plated layer 33, a plated metal pools in the plating reservoir S. The at least one plated layer 33 may work to reduce to some extent a height difference between a soldering electrode portion 21, 23, 27, 33 and the insulating protective layer 15.
    Type: Application
    Filed: June 1, 2009
    Publication date: April 7, 2011
    Applicant: HOKURIKU ELECTRIC INDUSTRY CO., LTD.
    Inventors: Katsumi Takeuchi, Yutaka Nomura, Hiroyuki Kurokawa
  • Patent number: 7825769
    Abstract: A terminal structure of a chip-like electric component capable of blocking entry of electromigration-causing factors through an insulating resin layer in the vicinity of the peak of a raised portion of an electrical element forming layer is obtained. A metal-glaze-based front electrode 103 containing silver is provided on a surface of an insulating ceramic substrate 101. A resistor layer 107 electrically connected to the front electrode 103 is provided on the substrate surface. A glass layer 109a is provided to completely cover a surface of the resistor layer 107 as well as a surface of an end portion of the resistor layer 107 and also to partially cover the front electrode 103. An insulating resin layer 109b is provided to cover a surface of the glass layer 109a as well as a surface of at least an end portion of the glass layer 109a and to partially cover the front electrode 103.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 2, 2010
    Assignee: Hokuriku Electric Co., Ltd.
    Inventors: Yutaka Nomura, Katsumi Takeuchi
  • Publication number: 20100266753
    Abstract: The present invention provides a connector chip capable of preventing electrical shorting between adjoining electrodes and also capable of readily connecting a plurality of electrodes on a first circuit substrate and a plurality of electrodes on a second circuit substrate without using a dedicated mounting device or the like. A plurality of conductive paths 5 are formed on an outer periphery surface constituted by continuous four surfaces 9A to 9D of an insulating substrate 3 including six surfaces of the surfaces 9A to 9D and surfaces 9E and 9F. Each of the conductive paths 5 goes round on the outer periphery surface. The conductive paths 5 are formed on the outer periphery surface at a predetermined interval in an opposing direction in which the remaining two surfaces 9E and 9F are opposing to each other. Each of insulating layers 7 having a property of repelling molten solder is formed between portions of each two adjoining conductive paths located on a pair of the surfaces 9A and 9B.
    Type: Application
    Filed: June 30, 2010
    Publication date: October 21, 2010
    Applicant: HOKURIKU ELECTRIC INDUSTRY CO., LTD.
    Inventors: Shinji Okamoto, Katsumi Takeuchi, Yutaka Nomura
  • Publication number: 20090231086
    Abstract: A terminal structure of a chip-like electric component capable of blocking entry of electromigration-causing factors through an insulating resin layer in the vicinity of the peak of a raised portion of an electrical element forming layer is obtained. A metal-glaze-based front electrode 103 containing silver is provided on a surface of an insulating ceramic substrate 101. A resistor layer 107 electrically connected to the front electrode 103 is provided on the substrate surface. A glass layer 109a is provided to completely cover a surface of the resistor layer 107 as well as a surface of an end portion of the resistor layer 107 and also to partially cover the front electrode 103. An insulating resin layer 109b is provided to cover a surface of the glass layer 109a as well as a surface of at least an end portion of the glass layer 109a and to partially cover the front electrode 103.
    Type: Application
    Filed: September 27, 2006
    Publication date: September 17, 2009
    Applicant: HOKURIKU ELECTRIC INDUSTRY CO., LTD.
    Inventors: Yutaka Nomura, Katsumi Takeuchi
  • Publication number: 20070072454
    Abstract: The present invention provides a connector chip capable of preventing electrical shorting between adjoining electrodes and also capable of readily connecting a plurality of electrodes on a first circuit substrate and a plurality of electrodes on a second circuit substrate without using a dedicated mounting device or the like. A plurality of conductive paths 5 are formed on an outer periphery surface constituted by continuous four surfaces 9A to 9D of an insulating substrate 3 including six surfaces of the surfaces 9A to 9D and surfaces 9E and 9F. Each of the conductive paths 5 goes round on the outer periphery surface. The conductive paths 5 are formed on the outer periphery surface at a predetermined interval in an opposing direction in which the remaining two surfaces 9E and 9F are opposing to each other. Each of insulating layers 7 having a property of repelling molten solder is formed between portions of each two adjoining conductive paths located on a pair of the surfaces 9A and 9B.
    Type: Application
    Filed: November 12, 2004
    Publication date: March 29, 2007
    Applicant: HOKURIKU ELECTRIC INDUSTRY CO., LTD.
    Inventors: Shinji Okamoto, Katsumi Takeuchi, Yutaka Nomura
  • Patent number: 6121394
    Abstract: The present invention is directed to a method for polymerizing an .alpha.-olefin characterized by using a catalyst system which is obtained by reacting a halogenated metallocene compound with an organometallic compound, and then bringing the resultant reaction product into contact with a compound which will be a stable anion by reaction with the reaction product of the halogenated metallocene compound and the organometallic compound.When the method of the present invention is carried out, a polyolefin can be obtained by the use of the inexpensive catalyst in a high activity per unit amount of the catalyst.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: September 19, 2000
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Ryuichi Sugimoto, Tadashi Asanuma, Tutomu Iwatani, Katsumi Takeuchi, Osamu Uchida
  • Patent number: 6005474
    Abstract: A chip-like network resistor is disclosed which is reduced in variation in resistance of terminal electrodes. A substrate (1) is formed on both ends (3, 5) with a plurality of recesses (7), at each of which a terminal electrode (17) connected to a thick-film electrode (9) is arranged. The terminal electrodes (17) each are constituted of a thin metal film electrode layer (19) and two plated layers (21, 23). The thin metal film electrode layer (19) includes a front surface electrode section (19a) formed on a front surface (1a) of the substrate (1) so as to overlap with the thick-film electrode (9), a side surface electrode section (19b) connected to the front surface electrode section (19a) and arranged so as to entirely cover an inner surface of the recess (7) and a rear surface electrode section (19c) formed on a rear surface (1b) of the substrate (1) and connected to the side surface electrode section (19b).
    Type: Grant
    Filed: August 27, 1998
    Date of Patent: December 21, 1999
    Assignee: Hokuriku Electric Industry Co., Ltd.
    Inventors: Katsumi Takeuchi, Mahito Shimada
  • Patent number: 5314956
    Abstract: Disclosed herein is a polypropylene resin composition of a high syndiotacticity comprising a substantial homopolymer of propylene, in which the ratio of the intensity of the peak attributable to the syndiotactic pentad bonds to the sum of the intensities of all the peaks attributable to the methyl groups in the spectrum of the methyl groups measured by .sup.13 C-NMR is 0.7 or more, and a copolymer of ethylene and propylene, and a preparation process thereof.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: May 24, 1994
    Assignee: Mitsui Toatsu Chemicals, Incorporated
    Inventors: Tadashi Asanuma, Tetsunosuke Shiomura, Nobutaka Uchikawa, Tutomu Iwatani, Katsumi Takeuchi
  • Patent number: 5212247
    Abstract: Disclosed herein is a polypropylene resin composition of a high syndiotacticity comprising a substantial homopolymer of propylene, in which the ratio of the intensity of the peak attributable to the syndiotactic pentad bonds to the sum of the intensities of all the peaks attributable to the methyl groups in the spectrum of the methyl groups measured by .sup.13 C-NMR is 0.7 or more, and a copolymer of ethylene and propylene, and a preparation process thereof.
    Type: Grant
    Filed: June 6, 1990
    Date of Patent: May 18, 1993
    Assignee: Mitsui Toatsu Chemicals, Inc.
    Inventors: Tadashi Asanuma, Tetsunosuke Shiomura, Nobutaka Uchikawa, Tutomu Iwatani, Katsumi Takeuchi