Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

Abstract: A semiconductor device includes: a local memory outputting a plurality of pieces of weight data in parallel; a plurality of product-sum operation units corresponding to the plurality of pieces of weight data; and a plurality of unit selectors corresponding to the product-sum operations units, supplied with a plurality of pieces of input data in parallel, selecting the one piece of input data from the supplied plurality of pieces of input data according to a plurality of pieces of additional information each indicating a position of the input data to be calculated with the corresponding product-sum arithmetic unit calculator in the pieces of input data, and outputting the selected input data. Each of the plurality of product-sum arithmetic units performs a product-sum operation between the weight data different from each other in the plurality of pieces of weight data and the input data outputted from the corresponding unit selector.

Abstract: A semiconductor device includes a data path having a plurality of processor elements, a state transition management unit managing a state of the data path, and a parallel computing unit in which an input and an output of data is sequentially carried out, and an output of the parallel computing unit is capable of being handled by the plurality of processor elements.

Abstract: A semiconductor device and method includes a configuration information storage memory that stores a plurality of configuration information items, a state transition management unit that selects any one of the plurality of configuration information items, and a data path unit that dynamically reconfigures a circuit according to the configuration information item selected by the state transition management unit. When a detection of a failure or no failure is made in any one of a plurality of logic circuit groups provided in the data path unit, the state transition management unit selects the configuration information item depending on a result of the detection.

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

Abstract: A semiconductor device and method includes a configuration information storage memory that stores a plurality of configuration information items, a state transition management unit that selects any one of the plurality of configuration information items, and a data path unit that dynamically reconfigures a circuit according to the configuration information item selected by the state transition management unit. When a detection of a failure or no failure is made in any one of a plurality of logic circuit groups provided in the data path unit, the state transition management unit selects the configuration information item depending on a result of the detection.

Abstract: According to an embodiment, a reconfigurable device 1 includes a configuration information storage memory 12, a state transition management unit 11, and a data path unit 13. When a failure is not detected in either of tiles T1 and T2 provided in the data path unit 13, the state transition management unit 11 selects the configuration information item so that a first processing circuit is configured using the tiles T1 and T2, while when a failure is detected in the tile T2, the state transition management unit 11 selects the configuration information item so that after a first intermediate processing circuit is configured using the tile T1 in which no failure is detected, a second intermediate processing circuit is configured again using the tile T1 in order to achieve the first processing circuit.

Abstract: According to an embodiment, a reconfigurable device 1 includes a configuration information storage memory 12, a state transition management unit 11, and a data path unit 13. When a failure is not detected in either of tiles T1 and T2 provided in the data path unit 13, the state transition management unit 11 selects the configuration information item so that a first processing circuit is configured using the tiles T1 and T2, while when a failure is detected in the tile T2, the state transition management unit 11 selects the configuration information item so that after a first intermediate processing circuit is configured using the tile T1 in which no failure is detected, a second intermediate processing circuit is configured again using the tile T1 in order to achieve the first processing circuit.

Abstract: An array type processor comprises a data path unit to execute processing, and a state management unit to control the state of the data path unit in accordance with a command that specifies processing on the data. An input DMA circuit reads from a memory information and data to be processed including a command corresponding to the data. The input DMA circuit first transfers the command to the state management unit, and then transfers the data to be processed to the data path unit.

Abstract: A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A stream processor for performing a plurality of processes parallel to each other on the data to be processed acquires a descriptor from the memory, reads data to be processed from the memory according to the input address information contained in the descriptor, processes the data, and stores the processed data back into the memory according to the output address information contained in the descriptor.

Abstract: In an information processing apparatus, a descriptor queue forming unit forms descriptors each including one task command for designating one task program and corresponding to one task data processed by the program, forms descriptor columns each formed by linking at least two of the descriptors including the same task command, and forms descriptor queues each formed by linking the descriptor columns. A memory stores the task data and the descriptor queues. A stream processor sequentially reads the descriptors from the memory in accordance with a structure of the descriptor queues and perform processings upon the task data corresponding to the read descriptors, respectively, using respective ones of the programs indicated by the task commands of the read descriptors, respectively.

Abstract: In a stream processor, an input direct memory access circuit is adapted to receive a task command and task data in correspondence with a task from an external memory. A processor unit is adapted to receive the task command and the task data from the input direct memory access circuit and perform the task upon the task data in accordance with a task program designated by the task command. A direct memory access controller is adapted to load the task program from the external memory into the processor unit upon receipt of a task program load request from the processor unit.

Abstract: An array type processor comprises a data path unit to execute processing, and a state management unit to control the state of the data path unit in accordance with a command that specifies processing on the data. An input DMA circuit reads from a memory information and data to be processed including a command corresponding to the data. The input DMA circuit first transfers the command to the state management unit, and then transfers the data to be processed to the data path unit.

Abstract: A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A stream processor for performing a plurality of processes parallel to each other on the data to be processed acquires a descriptor from the memory, reads data to be processed from the memory according to the input address information contained in the descriptor, processes the data, and stores the processed data back into the memory according to the output address information contained in the descriptor.