Abstract: According to one aspect, a semiconductor device includes: a buffer layer disposed on a front surface of a second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening, wherein the buffer layer has a higher Vickers hardness than the electrode, and a width w of each of the at least one opening satisfies w<Wth, where s is a thickness of the buffer layer, t is a thickness of the electrode, and Wth=2×(s×t?s2)0.5 holds true.

Abstract: A method for automatically arranging parts on a CAD comprises: part condition acquisition step A; part arrangement order acquisition step; boundary line acquisition step B; part arrangement step C; boundary line updating step; first repetition step; part type change step; and second repetition step. In step A, part boundary condition, set for each of types of parts, representing the type of the part to be permitted to be arranged adjacent to the part is acquired. In step B, boundary line boundary condition to be set for a boundary line parallel to an area termination end line of an arrangement area in X- or Y-direction is acquired. In step C, the part boundary condition set for the part and the boundary line boundary condition set for the boundary line arranged in the arrangement area are compared with each other, and the part is arranged when the conditions match each other.

Abstract: A SEB resistance evaluation method includes: disposing an excitation source within a model of a semiconductor device; and determining an energy of the excitation source at which the semiconductor device exhibits thermal runaway, while varying a voltage applied to the model of the semiconductor device and the energy of the excitation source.

Abstract: According to one aspect, a semiconductor device includes: a buffer layer disposed on a front surface of a second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening, wherein the buffer layer has a higher Vickers hardness than the electrode, and a width w of each of the at least one opening satisfies w<Wth, where s is a thickness of the buffer layer, t is a thickness of the electrode, and Wth=2×(s×t?s2)0.5 holds true.

Abstract: A SEB resistance evaluation method includes: disposing an excitation source within a model of a semiconductor device; and determining an energy of the excitation source at which the semiconductor device exhibits thermal runaway, while varying a voltage applied to the model of the semiconductor device and the energy of the excitation source.

Abstract: The object is to provide a technique for adjusting a turn-on operation and a turn-off operation of a transistor independently from each other in simulation for evaluating characteristics of the transistor. A simulation circuit for simulation for evaluating characteristics of a transistor includes a gate power supply configured to apply a voltage to a gate terminal of the transistor, a first diode connected between the gate terminal and the gate power supply, and a second diode connected in antiparallel with the first diode.

Abstract: The object is to provide a technique for adjusting a turn-on operation and a turn-off operation of a transistor independently from each other in simulation for evaluating characteristics of the transistor. A simulation circuit for simulation for evaluating characteristics of a transistor includes a gate power supply configured to apply a voltage to a gate terminal of the transistor, a first diode connected between the gate terminal and the gate power supply, and a second diode connected in antiparallel with the first diode.

Abstract: A semiconductor device includes a switching device region including an active region having a first conductivity-type emitter region formed on an upper surface side of a first conductivity-type substrate, a second conductivity-type base region formed on an upper surface side of the substrate, a second conductivity-type collector layer formed on a lower surface side of the substrate, and a diode region having a second conductivity-type anode layer formed on the upper surface side of the substrate and a first conductivity-type cathode layer formed on the lower surface side of the substrate, wherein the cathode layer is separated from the active region when planarly viewed, and on an upper surface side of the active region, a second conductivity type high-concentration region having an impurity concentration higher than that of the anode layer is formed.

Abstract: A semiconductor device includes a switching device region including an active region having a first conductivity-type emitter region formed on an upper surface side of a first conductivity-type substrate, a second conductivity-type base region formed on an upper surface side of the substrate, a second conductivity-type collector layer formed on a lower surface side of the substrate, and a diode region having a second conductivity-type anode layer formed on the upper surface side of the substrate and a first conductivity-type cathode layer formed on the lower surface side of the substrate, wherein the cathode layer is separated from the active region when planarly viewed, and on an upper surface side of the active region, a second conductivity type high-concentration region having an impurity concentration higher than that of the anode layer is formed.