Patents by Inventor Katsushi Mikuni
Katsushi Mikuni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10776556Abstract: A wiring board design support apparatus, in which a plurality of vias are arranged on a wiring board, includes a design information storage unit that stores design information of vias and wirings to be arranged on the wiring board, and a wiring board via arrangement unit that moves, on a basis of the design information, positions of lattice points arranged with same intervals in vertical and horizontal directions by a given moving amount in a vertical direction and a horizontal direction while alternately changing a moving direction in the horizontal direction of the lattice points for each row of the lattice and alternately changing a moving direction in the vertical direction of the lattice points for each column of the lattice, so as to arrange vias at positions of the lattice points after movement.Type: GrantFiled: June 27, 2019Date of Patent: September 15, 2020Assignee: KABUSHIKI KAISHA NIHON MICRONICSInventors: Katsushi Mikuni, Ryuichi Yagisawa, Akitsugu Yamaguchi
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Publication number: 20200050732Abstract: To improve wiring housing property, with preferable work efficiency, without deviation in the vertical direction or the horizontal direction, without expanding via arrangement areas.Type: ApplicationFiled: June 27, 2019Publication date: February 13, 2020Applicant: KABUSHIKI KAISHA NIHON MICRONICSInventors: KATSUSHI MIKUNI, RYUICHI YAGISAWA, AKITSUGU YAMAGUCHI
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Patent number: 9110098Abstract: Provided is a probe card capable of effectively placing electronic parts. A probe card according to the present invention includes a plurality of probes that come into contact with a plurality of electrodes of a device, a probe board including the plurality of probes provided thereon, a wiring board that is placed facing a surface of the probe board opposite to a surface including the probes provided thereon, a connector that includes a connection pin and a holder, in which the connection pin electrically connects a line of the probe board and a line of the wiring board, and the holder holds the connection pin between the probe board and the wiring board, and a first electronic part that is mounted on a probe board side surface of the wiring board and placed in a mounting space formed by a through hole or a recess provided in the holder.Type: GrantFiled: June 28, 2013Date of Patent: August 18, 2015Assignee: Kabushiki Kaisha Nihon MicronicsInventors: Katsushi Mikuni, Yoshinori Kikuchi, Yoshihito Onuma, Toshiyuki Kudo
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Patent number: 9095071Abstract: Provided is a method for manufacturing a multi-layer wiring board and the multi-layer wiring board that are capable of suppressing variation in resistance values. The method according to the present invention is the method for manufacturing a multi-layer wiring board. The method includes forming a resistor thin film, measuring resistance distribution of the resistor thin film, calculating resistor width adjustment rates of the plurality of resistors according to the resistance distribution, forming a pattern of a protective film on the resistor thin film, in which the pattern of the protective pattern has pattern width according to the resistor width adjustment rate, forming a pattern of a plating film on the resistor thin film at a position exposed from the protective film, and etching the resistor thin film at a position exposed from the plating film and the protective film so as to pattern the resistor thin film.Type: GrantFiled: November 13, 2013Date of Patent: July 28, 2015Assignee: KABUSHIKI KAISHA NIHON MICRONICSInventors: Yoshiyuki Fukami, Toshinori Omori, Katsushi Mikuni, Noriko Kon
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Publication number: 20140138139Abstract: Provided is a method for manufacturing a multi-layer wiring board and the multi-layer wiring board that are capable of suppressing variation in resistance values. The method according to the present invention is the method for manufacturing a multi-layer wiring board. The method includes forming a resistor thin film, measuring resistance distribution of the resistor thin film, calculating resistor width adjustment rates of the plurality of resistors according to the resistance distribution, forming a pattern of a protective film on the resistor thin film, in which the pattern of the protective pattern has pattern width according to the resistor width adjustment rate, forming a pattern of a plating film on the resistor thin film at a position exposed from the protective film, and etching the resistor thin film at a position exposed from the plating film and the protective film so as to pattern the resistor thin film.Type: ApplicationFiled: November 13, 2013Publication date: May 22, 2014Applicant: KABUSHIKI KAISHA NIHON MICRONICSInventors: Yoshiyuki FUKAMI, Toshinori OMORI, Katsushi MIKUNI, Noriko KON
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Publication number: 20140028341Abstract: Provided is a probe card capable of effectively placing electronic parts. A probe card according to the present invention includes a plurality of probes that come into contact with a plurality of electrodes of a device, a probe board including the plurality of probes provided thereon, a wiring board that is placed facing a surface of the probe board opposite to a surface including the probes provided thereon, a connector that includes a connection pin and a holder, in which the connection pin electrically connects a line of the probe board and a line of the wiring board, and the holder holds the connection pin between the probe board and the wiring board, and a first electronic part that is mounted on a probe board side surface of the wiring board and placed in a mounting space formed by a through hole or a recess provided in the holder.Type: ApplicationFiled: June 28, 2013Publication date: January 30, 2014Inventors: Katsushi MIKUNI, Yoshinori KIKUCHI, Yoshihito ONUMA, Toshiyuki KUDO
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Patent number: 8365130Abstract: A computer program generates a wire routing pattern that connects one driver with a plurality of receivers. The overlapping length of each vector pair, which consists of any two vectors headed from the driver to the receivers, is calculated. One vector pair that has the greatest overlapping length is selected. For the selected vector pair, three kinds of common nodes are created, each of which is used to make a common path part of the way to the receivers, to generate three kinds of renewed vector patterns. The operations are repeated and plural candidate routing patters are acquired. One candidate routing pattern having the smallest total wiring length is selected as the optimum routing pattern. If there exist plural patterns that have the same smallest total wiring length, one pattern can be selected that has the smallest one of the greatest. D-R path lengths.Type: GrantFiled: December 28, 2011Date of Patent: January 29, 2013Assignee: Micronics Japan Co., Ltd.Inventors: Katsushi Mikuni, Toshiyuki Kudo, Masatoshi Yokouchi, Issei Sakurada, Tatsuo Inoue
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Publication number: 20120167032Abstract: A computer program generates a wire routing pattern that connects one driver with a plurality of receivers. The overlapping length of each vector pair, which consists of any two vectors headed from the driver to the receivers, is calculated. One vector pair that has the greatest overlapping length is selected. For the selected vector pair, three kinds of common nodes are created, each of which is used to make a common path part of the way to the receivers, to generate three kinds of renewed vector patterns. The operations are repeated and plural candidate routing patters are acquired. One candidate routing pattern having the smallest total wiring length is selected as the optimum routing pattern. If there exist plural patterns that have the same smallest total wiring length, one pattern can be selected that has the smallest one of the greatest D-R path lengths.Type: ApplicationFiled: December 28, 2011Publication date: June 28, 2012Applicant: MICRONICS JAPAN CO., LTD.Inventors: Katsushi Mikuni, Toshiyuki Kudo, Masatoshi Yokouchi, Issei Sakurada, Tatsuo Inoue
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Patent number: 7735221Abstract: A method of manufacturing a multilayer wiring board is provided. A flat surface is formed on a surface of a multilayer wiring layer, and resistive material is deposited on the flat surface. The multilayer wiring board comprises a multilayer wiring layer on whose surface convexo-concave is formed, a dummy layer burying the convexo-concave, a resistance material layer made of an electrical resistance material deposited on the dummy layer and at an area going beyond the dummy layer, and a wire made of a conductive material deposited on the resistance material layer and ranging from the area going beyond the dummy layer to a part of the flat surface area of the dummy layer, wherein a resistive element is formed at an area of the resistance material layer that the wire does not reach.Type: GrantFiled: April 8, 2008Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha Nihon MicronicsInventors: Tatsuo Inoue, Osamu Arai, Katsushi Mikuni, Norihiro Imai
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Publication number: 20090015276Abstract: A method of producing a probe assembly which uses thermal energy of a laser light for bonding a plurality of connection pads provided on a probe board and a probe disposed on each connection pad. In the neighborhood of at least one of the connection pads on the probe board, a dummy connection pad with no probe adhered is formed in order to uniform the thermal energy by irradiation of each bonding portion of each connection pad and the corresponding probe.Type: ApplicationFiled: June 26, 2008Publication date: January 15, 2009Applicant: KABUSHIKI KAISHA NIHON MICRONICSInventors: Masatoshi YOKOUCHI, Katsushi MIKUNI, Masahisa TAZAWA, Norihiro IMAI
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Publication number: 20080315901Abstract: The present invention provides a multilayer wiring board in which resistive elements each of whose error from a desired value is smaller than in a conventional case are built, a method for manufacturing the same, and a probe apparatus utilizing the multilayer wiring board. The present invention is based on a basic concept of forming a flat surface on a surface of a multilayer wiring layer on which a resistive element material is to be deposited and depositing the resistive element material on the flat surface.Type: ApplicationFiled: April 8, 2008Publication date: December 25, 2008Applicant: Kabushiki Kaisha Nihon MicronicsInventors: Tatsuo INOUE, Osamu ARAI, Katsushi MIKUNI, Norihiro IMAI